1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 * Andreas Hansson
51 */
52
53#ifndef __ARCH_X86_INTERRUPTS_HH__
54#define __ARCH_X86_INTERRUPTS_HH__
55
56#include "arch/x86/regs/apic.hh"
57#include "arch/x86/faults.hh"
58#include "arch/x86/intmessage.hh"
59#include "base/bitfield.hh"
60#include "cpu/thread_context.hh"
61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69int divideFromConf(uint32_t conf);
70
71namespace X86ISA {
72
73ApicRegIndex decodeAddr(Addr paddr);
74
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 * Andreas Hansson
51 */
52
53#ifndef __ARCH_X86_INTERRUPTS_HH__
54#define __ARCH_X86_INTERRUPTS_HH__
55
56#include "arch/x86/regs/apic.hh"
57#include "arch/x86/faults.hh"
58#include "arch/x86/intmessage.hh"
59#include "base/bitfield.hh"
60#include "cpu/thread_context.hh"
61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69int divideFromConf(uint32_t conf);
70
71namespace X86ISA {
72
73ApicRegIndex decodeAddr(Addr paddr);
74
|
75class Interrupts : public BasicPioDevice, IntDev
| 75class Interrupts : public BasicPioDevice, IntDevice
|
76{
77 protected:
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
80
81 BitUnion32(LVTEntry)
82 Bitfield<7, 0> vector;
83 Bitfield<10, 8> deliveryMode;
84 Bitfield<12> status;
85 Bitfield<13> polarity;
86 Bitfield<14> remoteIRR;
87 Bitfield<15> trigger;
88 Bitfield<16> masked;
89 Bitfield<17> periodic;
90 EndBitUnion(LVTEntry)
91
92 /*
93 * Timing related stuff.
94 */
95 class ApicTimerEvent : public Event
96 {
97 private:
98 Interrupts *localApic;
99 public:
100 ApicTimerEvent(Interrupts *_localApic) :
101 Event(), localApic(_localApic)
102 {}
103
104 void process()
105 {
106 assert(localApic);
107 if (localApic->triggerTimerInterrupt()) {
108 localApic->setReg(APIC_INITIAL_COUNT,
109 localApic->readReg(APIC_INITIAL_COUNT));
110 }
111 }
112 };
113
114 ApicTimerEvent apicTimerEvent;
115
116 /*
117 * A set of variables to keep track of interrupts that don't go through
118 * the IRR.
119 */
120 bool pendingSmi;
121 uint8_t smiVector;
122 bool pendingNmi;
123 uint8_t nmiVector;
124 bool pendingExtInt;
125 uint8_t extIntVector;
126 bool pendingInit;
127 uint8_t initVector;
128 bool pendingStartup;
129 uint8_t startupVector;
130 bool startedUp;
131
132 // This is a quick check whether any of the above (except ExtInt) are set.
133 bool pendingUnmaskableInt;
134
135 // A count of how many IPIs are in flight.
136 int pendingIPIs;
137
138 /*
139 * IRR and ISR maintenance.
140 */
141 uint8_t IRRV;
142 uint8_t ISRV;
143
144 int
145 findRegArrayMSB(ApicRegIndex base)
146 {
147 int offset = 7;
148 do {
149 if (regs[base + offset] != 0) {
150 return offset * 32 + findMsbSet(regs[base + offset]);
151 }
152 } while (offset--);
153 return 0;
154 }
155
156 void
157 updateIRRV()
158 {
159 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
160 }
161
162 void
163 updateISRV()
164 {
165 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
166 }
167
168 void
169 setRegArrayBit(ApicRegIndex base, uint8_t vector)
170 {
171 regs[base + (vector / 32)] |= (1 << (vector % 32));
172 }
173
174 void
175 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
176 {
177 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
178 }
179
180 bool
181 getRegArrayBit(ApicRegIndex base, uint8_t vector)
182 {
183 return bits(regs[base + (vector / 32)], vector % 5);
184 }
185
186 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
187
188 BaseCPU *cpu;
189
190 int initialApicId;
191
192 // Port for receiving interrupts
193 IntSlavePort intSlavePort;
194
195 public:
196
197 int getInitialApicId() { return initialApicId; }
198
199 /*
200 * Params stuff.
201 */
202 typedef X86LocalApicParams Params;
203
204 void setCPU(BaseCPU * newCPU);
205
206 const Params *
207 params() const
208 {
209 return dynamic_cast<const Params *>(_params);
210 }
211
212 /*
213 * Initialize this object by registering it with the IO APIC.
214 */
215 void init();
216
217 /*
| 76{
77 protected:
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
80
81 BitUnion32(LVTEntry)
82 Bitfield<7, 0> vector;
83 Bitfield<10, 8> deliveryMode;
84 Bitfield<12> status;
85 Bitfield<13> polarity;
86 Bitfield<14> remoteIRR;
87 Bitfield<15> trigger;
88 Bitfield<16> masked;
89 Bitfield<17> periodic;
90 EndBitUnion(LVTEntry)
91
92 /*
93 * Timing related stuff.
94 */
95 class ApicTimerEvent : public Event
96 {
97 private:
98 Interrupts *localApic;
99 public:
100 ApicTimerEvent(Interrupts *_localApic) :
101 Event(), localApic(_localApic)
102 {}
103
104 void process()
105 {
106 assert(localApic);
107 if (localApic->triggerTimerInterrupt()) {
108 localApic->setReg(APIC_INITIAL_COUNT,
109 localApic->readReg(APIC_INITIAL_COUNT));
110 }
111 }
112 };
113
114 ApicTimerEvent apicTimerEvent;
115
116 /*
117 * A set of variables to keep track of interrupts that don't go through
118 * the IRR.
119 */
120 bool pendingSmi;
121 uint8_t smiVector;
122 bool pendingNmi;
123 uint8_t nmiVector;
124 bool pendingExtInt;
125 uint8_t extIntVector;
126 bool pendingInit;
127 uint8_t initVector;
128 bool pendingStartup;
129 uint8_t startupVector;
130 bool startedUp;
131
132 // This is a quick check whether any of the above (except ExtInt) are set.
133 bool pendingUnmaskableInt;
134
135 // A count of how many IPIs are in flight.
136 int pendingIPIs;
137
138 /*
139 * IRR and ISR maintenance.
140 */
141 uint8_t IRRV;
142 uint8_t ISRV;
143
144 int
145 findRegArrayMSB(ApicRegIndex base)
146 {
147 int offset = 7;
148 do {
149 if (regs[base + offset] != 0) {
150 return offset * 32 + findMsbSet(regs[base + offset]);
151 }
152 } while (offset--);
153 return 0;
154 }
155
156 void
157 updateIRRV()
158 {
159 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
160 }
161
162 void
163 updateISRV()
164 {
165 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
166 }
167
168 void
169 setRegArrayBit(ApicRegIndex base, uint8_t vector)
170 {
171 regs[base + (vector / 32)] |= (1 << (vector % 32));
172 }
173
174 void
175 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
176 {
177 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
178 }
179
180 bool
181 getRegArrayBit(ApicRegIndex base, uint8_t vector)
182 {
183 return bits(regs[base + (vector / 32)], vector % 5);
184 }
185
186 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
187
188 BaseCPU *cpu;
189
190 int initialApicId;
191
192 // Port for receiving interrupts
193 IntSlavePort intSlavePort;
194
195 public:
196
197 int getInitialApicId() { return initialApicId; }
198
199 /*
200 * Params stuff.
201 */
202 typedef X86LocalApicParams Params;
203
204 void setCPU(BaseCPU * newCPU);
205
206 const Params *
207 params() const
208 {
209 return dynamic_cast<const Params *>(_params);
210 }
211
212 /*
213 * Initialize this object by registering it with the IO APIC.
214 */
215 void init();
216
217 /*
|
218 * Functions to interact with the interrupt port from IntDev.
| 218 * Functions to interact with the interrupt port from IntDevice.
|
219 */
220 Tick read(PacketPtr pkt);
221 Tick write(PacketPtr pkt);
222 Tick recvMessage(PacketPtr pkt);
223 Tick recvResponse(PacketPtr pkt);
224
225 bool
226 triggerTimerInterrupt()
227 {
228 LVTEntry entry = regs[APIC_LVT_TIMER];
229 if (!entry.masked)
230 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
231 return entry.periodic;
232 }
233
234 AddrRangeList getIntAddrRange() const;
235
236 BaseMasterPort &getMasterPort(const std::string &if_name,
237 PortID idx = InvalidPortID)
238 {
239 if (if_name == "int_master") {
240 return intMasterPort;
241 }
242 return BasicPioDevice::getMasterPort(if_name, idx);
243 }
244
245 BaseSlavePort &getSlavePort(const std::string &if_name,
246 PortID idx = InvalidPortID)
247 {
248 if (if_name == "int_slave") {
249 return intSlavePort;
250 }
251 return BasicPioDevice::getSlavePort(if_name, idx);
252 }
253
254 /*
255 * Functions to access and manipulate the APIC's registers.
256 */
257
258 uint32_t readReg(ApicRegIndex miscReg);
259 void setReg(ApicRegIndex reg, uint32_t val);
260 void
261 setRegNoEffect(ApicRegIndex reg, uint32_t val)
262 {
263 regs[reg] = val;
264 }
265
266 /*
267 * Constructor.
268 */
269
270 Interrupts(Params * p);
271
272 /*
273 * Functions for retrieving interrupts for the CPU to handle.
274 */
275
276 bool checkInterrupts(ThreadContext *tc) const;
277 Fault getInterrupt(ThreadContext *tc);
278 void updateIntrInfo(ThreadContext *tc);
279
280 /*
281 * Serialization.
282 */
283
284 virtual void serialize(std::ostream &os);
285 virtual void unserialize(Checkpoint *cp, const std::string §ion);
286
287 /*
288 * Old functions needed for compatability but which will be phased out
289 * eventually.
290 */
291 void
292 post(int int_num, int index)
293 {
294 panic("Interrupts::post unimplemented!\n");
295 }
296
297 void
298 clear(int int_num, int index)
299 {
300 panic("Interrupts::clear unimplemented!\n");
301 }
302
303 void
304 clearAll()
305 {
306 panic("Interrupts::clearAll unimplemented!\n");
307 }
308};
309
310} // namespace X86ISA
311
312#endif // __ARCH_X86_INTERRUPTS_HH__
| 219 */
220 Tick read(PacketPtr pkt);
221 Tick write(PacketPtr pkt);
222 Tick recvMessage(PacketPtr pkt);
223 Tick recvResponse(PacketPtr pkt);
224
225 bool
226 triggerTimerInterrupt()
227 {
228 LVTEntry entry = regs[APIC_LVT_TIMER];
229 if (!entry.masked)
230 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
231 return entry.periodic;
232 }
233
234 AddrRangeList getIntAddrRange() const;
235
236 BaseMasterPort &getMasterPort(const std::string &if_name,
237 PortID idx = InvalidPortID)
238 {
239 if (if_name == "int_master") {
240 return intMasterPort;
241 }
242 return BasicPioDevice::getMasterPort(if_name, idx);
243 }
244
245 BaseSlavePort &getSlavePort(const std::string &if_name,
246 PortID idx = InvalidPortID)
247 {
248 if (if_name == "int_slave") {
249 return intSlavePort;
250 }
251 return BasicPioDevice::getSlavePort(if_name, idx);
252 }
253
254 /*
255 * Functions to access and manipulate the APIC's registers.
256 */
257
258 uint32_t readReg(ApicRegIndex miscReg);
259 void setReg(ApicRegIndex reg, uint32_t val);
260 void
261 setRegNoEffect(ApicRegIndex reg, uint32_t val)
262 {
263 regs[reg] = val;
264 }
265
266 /*
267 * Constructor.
268 */
269
270 Interrupts(Params * p);
271
272 /*
273 * Functions for retrieving interrupts for the CPU to handle.
274 */
275
276 bool checkInterrupts(ThreadContext *tc) const;
277 Fault getInterrupt(ThreadContext *tc);
278 void updateIntrInfo(ThreadContext *tc);
279
280 /*
281 * Serialization.
282 */
283
284 virtual void serialize(std::ostream &os);
285 virtual void unserialize(Checkpoint *cp, const std::string §ion);
286
287 /*
288 * Old functions needed for compatability but which will be phased out
289 * eventually.
290 */
291 void
292 post(int int_num, int index)
293 {
294 panic("Interrupts::post unimplemented!\n");
295 }
296
297 void
298 clear(int int_num, int index)
299 {
300 panic("Interrupts::clear unimplemented!\n");
301 }
302
303 void
304 clearAll()
305 {
306 panic("Interrupts::clearAll unimplemented!\n");
307 }
308};
309
310} // namespace X86ISA
311
312#endif // __ARCH_X86_INTERRUPTS_HH__
|