1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_INTERRUPTS_HH__
41#define __ARCH_X86_INTERRUPTS_HH__
42
43#include "arch/x86/regs/apic.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/intmessage.hh"
46#include "base/bitfield.hh"
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_INTERRUPTS_HH__
41#define __ARCH_X86_INTERRUPTS_HH__
42
43#include "arch/x86/regs/apic.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/intmessage.hh"
46#include "base/bitfield.hh"
|
| 47#include "config/full_system.hh"
|
47#include "cpu/thread_context.hh"
48#include "dev/x86/intdev.hh"
49#include "dev/io_device.hh"
50#include "params/X86LocalApic.hh"
51#include "sim/eventq.hh"
52
53class ThreadContext;
54class BaseCPU;
55
56namespace X86ISA {
57
58class Interrupts : public BasicPioDevice, IntDev
59{
60 protected:
61 // Storage for the APIC registers
62 uint32_t regs[NUM_APIC_REGS];
63
64 BitUnion32(LVTEntry)
65 Bitfield<7, 0> vector;
66 Bitfield<10, 8> deliveryMode;
67 Bitfield<12> status;
68 Bitfield<13> polarity;
69 Bitfield<14> remoteIRR;
70 Bitfield<15> trigger;
71 Bitfield<16> masked;
72 Bitfield<17> periodic;
73 EndBitUnion(LVTEntry)
74
75 /*
76 * Timing related stuff.
77 */
78 Tick latency;
79 Tick clock;
80
81 class ApicTimerEvent : public Event
82 {
83 private:
84 Interrupts *localApic;
85 public:
86 ApicTimerEvent(Interrupts *_localApic) :
87 Event(), localApic(_localApic)
88 {}
89
90 void process()
91 {
92 assert(localApic);
93 if (localApic->triggerTimerInterrupt()) {
94 localApic->setReg(APIC_INITIAL_COUNT,
95 localApic->readReg(APIC_INITIAL_COUNT));
96 }
97 }
98 };
99
100 ApicTimerEvent apicTimerEvent;
101
102 /*
103 * A set of variables to keep track of interrupts that don't go through
104 * the IRR.
105 */
106 bool pendingSmi;
107 uint8_t smiVector;
108 bool pendingNmi;
109 uint8_t nmiVector;
110 bool pendingExtInt;
111 uint8_t extIntVector;
112 bool pendingInit;
113 uint8_t initVector;
114 bool pendingStartup;
115 uint8_t startupVector;
116 bool startedUp;
117
118 // This is a quick check whether any of the above (except ExtInt) are set.
119 bool pendingUnmaskableInt;
120
121 // A count of how many IPIs are in flight.
122 int pendingIPIs;
123
124 /*
125 * IRR and ISR maintenance.
126 */
127 uint8_t IRRV;
128 uint8_t ISRV;
129
130 int
131 findRegArrayMSB(ApicRegIndex base)
132 {
133 int offset = 7;
134 do {
135 if (regs[base + offset] != 0) {
136 return offset * 32 + findMsbSet(regs[base + offset]);
137 }
138 } while (offset--);
139 return 0;
140 }
141
142 void
143 updateIRRV()
144 {
145 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
146 }
147
148 void
149 updateISRV()
150 {
151 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
152 }
153
154 void
155 setRegArrayBit(ApicRegIndex base, uint8_t vector)
156 {
157 regs[base + (vector / 32)] |= (1 << (vector % 32));
158 }
159
160 void
161 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
162 {
163 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
164 }
165
166 bool
167 getRegArrayBit(ApicRegIndex base, uint8_t vector)
168 {
169 return bits(regs[base + (vector / 32)], vector % 5);
170 }
171
172 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
173
174 BaseCPU *cpu;
175
176 int initialApicId;
177
| 48#include "cpu/thread_context.hh"
49#include "dev/x86/intdev.hh"
50#include "dev/io_device.hh"
51#include "params/X86LocalApic.hh"
52#include "sim/eventq.hh"
53
54class ThreadContext;
55class BaseCPU;
56
57namespace X86ISA {
58
59class Interrupts : public BasicPioDevice, IntDev
60{
61 protected:
62 // Storage for the APIC registers
63 uint32_t regs[NUM_APIC_REGS];
64
65 BitUnion32(LVTEntry)
66 Bitfield<7, 0> vector;
67 Bitfield<10, 8> deliveryMode;
68 Bitfield<12> status;
69 Bitfield<13> polarity;
70 Bitfield<14> remoteIRR;
71 Bitfield<15> trigger;
72 Bitfield<16> masked;
73 Bitfield<17> periodic;
74 EndBitUnion(LVTEntry)
75
76 /*
77 * Timing related stuff.
78 */
79 Tick latency;
80 Tick clock;
81
82 class ApicTimerEvent : public Event
83 {
84 private:
85 Interrupts *localApic;
86 public:
87 ApicTimerEvent(Interrupts *_localApic) :
88 Event(), localApic(_localApic)
89 {}
90
91 void process()
92 {
93 assert(localApic);
94 if (localApic->triggerTimerInterrupt()) {
95 localApic->setReg(APIC_INITIAL_COUNT,
96 localApic->readReg(APIC_INITIAL_COUNT));
97 }
98 }
99 };
100
101 ApicTimerEvent apicTimerEvent;
102
103 /*
104 * A set of variables to keep track of interrupts that don't go through
105 * the IRR.
106 */
107 bool pendingSmi;
108 uint8_t smiVector;
109 bool pendingNmi;
110 uint8_t nmiVector;
111 bool pendingExtInt;
112 uint8_t extIntVector;
113 bool pendingInit;
114 uint8_t initVector;
115 bool pendingStartup;
116 uint8_t startupVector;
117 bool startedUp;
118
119 // This is a quick check whether any of the above (except ExtInt) are set.
120 bool pendingUnmaskableInt;
121
122 // A count of how many IPIs are in flight.
123 int pendingIPIs;
124
125 /*
126 * IRR and ISR maintenance.
127 */
128 uint8_t IRRV;
129 uint8_t ISRV;
130
131 int
132 findRegArrayMSB(ApicRegIndex base)
133 {
134 int offset = 7;
135 do {
136 if (regs[base + offset] != 0) {
137 return offset * 32 + findMsbSet(regs[base + offset]);
138 }
139 } while (offset--);
140 return 0;
141 }
142
143 void
144 updateIRRV()
145 {
146 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
147 }
148
149 void
150 updateISRV()
151 {
152 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
153 }
154
155 void
156 setRegArrayBit(ApicRegIndex base, uint8_t vector)
157 {
158 regs[base + (vector / 32)] |= (1 << (vector % 32));
159 }
160
161 void
162 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
163 {
164 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
165 }
166
167 bool
168 getRegArrayBit(ApicRegIndex base, uint8_t vector)
169 {
170 return bits(regs[base + (vector / 32)], vector % 5);
171 }
172
173 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
174
175 BaseCPU *cpu;
176
177 int initialApicId;
178
|
| 179#if FULL_SYSTEM
180 Platform *platform;
181#endif
182
|
178 public:
179 /*
180 * Params stuff.
181 */
182 typedef X86LocalApicParams Params;
183
184 void setCPU(BaseCPU * newCPU);
185
186 void
187 setClock(Tick newClock)
188 {
189 clock = newClock;
190 }
191
192 const Params *
193 params() const
194 {
195 return dynamic_cast<const Params *>(_params);
196 }
197
198 /*
199 * Initialize this object by registering it with the IO APIC.
200 */
201 void init();
202
203 /*
204 * Functions to interact with the interrupt port from IntDev.
205 */
206 Tick read(PacketPtr pkt);
207 Tick write(PacketPtr pkt);
208 Tick recvMessage(PacketPtr pkt);
209 Tick recvResponse(PacketPtr pkt);
210
211 bool
212 triggerTimerInterrupt()
213 {
214 LVTEntry entry = regs[APIC_LVT_TIMER];
215 if (!entry.masked)
216 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
217 return entry.periodic;
218 }
219
| 183 public:
184 /*
185 * Params stuff.
186 */
187 typedef X86LocalApicParams Params;
188
189 void setCPU(BaseCPU * newCPU);
190
191 void
192 setClock(Tick newClock)
193 {
194 clock = newClock;
195 }
196
197 const Params *
198 params() const
199 {
200 return dynamic_cast<const Params *>(_params);
201 }
202
203 /*
204 * Initialize this object by registering it with the IO APIC.
205 */
206 void init();
207
208 /*
209 * Functions to interact with the interrupt port from IntDev.
210 */
211 Tick read(PacketPtr pkt);
212 Tick write(PacketPtr pkt);
213 Tick recvMessage(PacketPtr pkt);
214 Tick recvResponse(PacketPtr pkt);
215
216 bool
217 triggerTimerInterrupt()
218 {
219 LVTEntry entry = regs[APIC_LVT_TIMER];
220 if (!entry.masked)
221 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
222 return entry.periodic;
223 }
224
|
220 AddrRangeList getAddrRanges();
221 AddrRangeList getIntAddrRange();
| 225 void addressRanges(AddrRangeList &range_list);
226 void getIntAddrRange(AddrRangeList &range_list);
|
222
223 Port *getPort(const std::string &if_name, int idx = -1)
224 {
225 if (if_name == "int_port")
226 return intPort;
227 return BasicPioDevice::getPort(if_name, idx);
228 }
229
230 /*
231 * Functions to access and manipulate the APIC's registers.
232 */
233
234 uint32_t readReg(ApicRegIndex miscReg);
235 void setReg(ApicRegIndex reg, uint32_t val);
236 void
237 setRegNoEffect(ApicRegIndex reg, uint32_t val)
238 {
239 regs[reg] = val;
240 }
241
242 /*
243 * Constructor.
244 */
245
246 Interrupts(Params * p);
247
248 /*
249 * Functions for retrieving interrupts for the CPU to handle.
250 */
251
252 bool checkInterrupts(ThreadContext *tc) const;
253 Fault getInterrupt(ThreadContext *tc);
254 void updateIntrInfo(ThreadContext *tc);
255
256 /*
257 * Serialization.
258 */
259
260 virtual void serialize(std::ostream &os);
261 virtual void unserialize(Checkpoint *cp, const std::string §ion);
262
263 /*
264 * Old functions needed for compatability but which will be phased out
265 * eventually.
266 */
267 void
268 post(int int_num, int index)
269 {
270 panic("Interrupts::post unimplemented!\n");
271 }
272
273 void
274 clear(int int_num, int index)
275 {
276 panic("Interrupts::clear unimplemented!\n");
277 }
278
279 void
280 clearAll()
281 {
282 panic("Interrupts::clearAll unimplemented!\n");
283 }
284};
285
286} // namespace X86ISA
287
288#endif // __ARCH_X86_INTERRUPTS_HH__
| 227
228 Port *getPort(const std::string &if_name, int idx = -1)
229 {
230 if (if_name == "int_port")
231 return intPort;
232 return BasicPioDevice::getPort(if_name, idx);
233 }
234
235 /*
236 * Functions to access and manipulate the APIC's registers.
237 */
238
239 uint32_t readReg(ApicRegIndex miscReg);
240 void setReg(ApicRegIndex reg, uint32_t val);
241 void
242 setRegNoEffect(ApicRegIndex reg, uint32_t val)
243 {
244 regs[reg] = val;
245 }
246
247 /*
248 * Constructor.
249 */
250
251 Interrupts(Params * p);
252
253 /*
254 * Functions for retrieving interrupts for the CPU to handle.
255 */
256
257 bool checkInterrupts(ThreadContext *tc) const;
258 Fault getInterrupt(ThreadContext *tc);
259 void updateIntrInfo(ThreadContext *tc);
260
261 /*
262 * Serialization.
263 */
264
265 virtual void serialize(std::ostream &os);
266 virtual void unserialize(Checkpoint *cp, const std::string §ion);
267
268 /*
269 * Old functions needed for compatability but which will be phased out
270 * eventually.
271 */
272 void
273 post(int int_num, int index)
274 {
275 panic("Interrupts::post unimplemented!\n");
276 }
277
278 void
279 clear(int int_num, int index)
280 {
281 panic("Interrupts::clear unimplemented!\n");
282 }
283
284 void
285 clearAll()
286 {
287 panic("Interrupts::clearAll unimplemented!\n");
288 }
289};
290
291} // namespace X86ISA
292
293#endif // __ARCH_X86_INTERRUPTS_HH__
|