1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72class BaseCPU;
73
74namespace X86ISA {
75
76class Interrupts : public BasicPioDevice, IntDev
77{
78 protected:
79 // Storage for the APIC registers
80 uint32_t regs[NUM_APIC_REGS];
81
82 BitUnion32(LVTEntry)
83 Bitfield<7, 0> vector;
84 Bitfield<10, 8> deliveryMode;
85 Bitfield<12> status;
86 Bitfield<13> polarity;
87 Bitfield<14> remoteIRR;
88 Bitfield<15> trigger;
89 Bitfield<16> masked;
90 Bitfield<17> periodic;
91 EndBitUnion(LVTEntry)
92
93 /*
94 * Timing related stuff.
95 */
96 Tick latency;
97 Tick clock;
98
99 class ApicTimerEvent : public Event
100 {
101 private:
102 Interrupts *localApic;
103 public:
104 ApicTimerEvent(Interrupts *_localApic) :
105 Event(), localApic(_localApic)
106 {}
107
108 void process()
109 {
110 assert(localApic);
111 if (localApic->triggerTimerInterrupt()) {
112 localApic->setReg(APIC_INITIAL_COUNT,
113 localApic->readReg(APIC_INITIAL_COUNT));
114 }
115 }
116 };
117
118 ApicTimerEvent apicTimerEvent;
119
120 /*
121 * A set of variables to keep track of interrupts that don't go through
122 * the IRR.
123 */
124 bool pendingSmi;
125 uint8_t smiVector;
126 bool pendingNmi;
127 uint8_t nmiVector;
128 bool pendingExtInt;
129 uint8_t extIntVector;
130 bool pendingInit;
131 uint8_t initVector;
132 bool pendingStartup;
133 uint8_t startupVector;
134 bool startedUp;
135
136 // This is a quick check whether any of the above (except ExtInt) are set.
137 bool pendingUnmaskableInt;
138
139 // A count of how many IPIs are in flight.
140 int pendingIPIs;
141
142 /*
143 * IRR and ISR maintenance.
144 */
145 uint8_t IRRV;
146 uint8_t ISRV;
147
148 int
149 findRegArrayMSB(ApicRegIndex base)
150 {
151 int offset = 7;
152 do {
153 if (regs[base + offset] != 0) {
154 return offset * 32 + findMsbSet(regs[base + offset]);
155 }
156 } while (offset--);
157 return 0;
158 }
159
160 void
161 updateIRRV()
162 {
163 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
164 }
165
166 void
167 updateISRV()
168 {
169 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
170 }
171
172 void
173 setRegArrayBit(ApicRegIndex base, uint8_t vector)
174 {
175 regs[base + (vector / 32)] |= (1 << (vector % 32));
176 }
177
178 void
179 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
180 {
181 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
182 }
183
184 bool
185 getRegArrayBit(ApicRegIndex base, uint8_t vector)
186 {
187 return bits(regs[base + (vector / 32)], vector % 5);
188 }
189
190 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
191
192 BaseCPU *cpu;
193
194 int initialApicId;
195
196 public:
197 /*
198 * Params stuff.
199 */
200 typedef X86LocalApicParams Params;
201
202 void setCPU(BaseCPU * newCPU);
203
204 void
205 setClock(Tick newClock)
206 {
207 clock = newClock;
208 }
209
210 const Params *
211 params() const
212 {
213 return dynamic_cast<const Params *>(_params);
214 }
215
216 /*
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72class BaseCPU;
73
74namespace X86ISA {
75
76class Interrupts : public BasicPioDevice, IntDev
77{
78 protected:
79 // Storage for the APIC registers
80 uint32_t regs[NUM_APIC_REGS];
81
82 BitUnion32(LVTEntry)
83 Bitfield<7, 0> vector;
84 Bitfield<10, 8> deliveryMode;
85 Bitfield<12> status;
86 Bitfield<13> polarity;
87 Bitfield<14> remoteIRR;
88 Bitfield<15> trigger;
89 Bitfield<16> masked;
90 Bitfield<17> periodic;
91 EndBitUnion(LVTEntry)
92
93 /*
94 * Timing related stuff.
95 */
96 Tick latency;
97 Tick clock;
98
99 class ApicTimerEvent : public Event
100 {
101 private:
102 Interrupts *localApic;
103 public:
104 ApicTimerEvent(Interrupts *_localApic) :
105 Event(), localApic(_localApic)
106 {}
107
108 void process()
109 {
110 assert(localApic);
111 if (localApic->triggerTimerInterrupt()) {
112 localApic->setReg(APIC_INITIAL_COUNT,
113 localApic->readReg(APIC_INITIAL_COUNT));
114 }
115 }
116 };
117
118 ApicTimerEvent apicTimerEvent;
119
120 /*
121 * A set of variables to keep track of interrupts that don't go through
122 * the IRR.
123 */
124 bool pendingSmi;
125 uint8_t smiVector;
126 bool pendingNmi;
127 uint8_t nmiVector;
128 bool pendingExtInt;
129 uint8_t extIntVector;
130 bool pendingInit;
131 uint8_t initVector;
132 bool pendingStartup;
133 uint8_t startupVector;
134 bool startedUp;
135
136 // This is a quick check whether any of the above (except ExtInt) are set.
137 bool pendingUnmaskableInt;
138
139 // A count of how many IPIs are in flight.
140 int pendingIPIs;
141
142 /*
143 * IRR and ISR maintenance.
144 */
145 uint8_t IRRV;
146 uint8_t ISRV;
147
148 int
149 findRegArrayMSB(ApicRegIndex base)
150 {
151 int offset = 7;
152 do {
153 if (regs[base + offset] != 0) {
154 return offset * 32 + findMsbSet(regs[base + offset]);
155 }
156 } while (offset--);
157 return 0;
158 }
159
160 void
161 updateIRRV()
162 {
163 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
164 }
165
166 void
167 updateISRV()
168 {
169 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
170 }
171
172 void
173 setRegArrayBit(ApicRegIndex base, uint8_t vector)
174 {
175 regs[base + (vector / 32)] |= (1 << (vector % 32));
176 }
177
178 void
179 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
180 {
181 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
182 }
183
184 bool
185 getRegArrayBit(ApicRegIndex base, uint8_t vector)
186 {
187 return bits(regs[base + (vector / 32)], vector % 5);
188 }
189
190 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
191
192 BaseCPU *cpu;
193
194 int initialApicId;
195
196 public:
197 /*
198 * Params stuff.
199 */
200 typedef X86LocalApicParams Params;
201
202 void setCPU(BaseCPU * newCPU);
203
204 void
205 setClock(Tick newClock)
206 {
207 clock = newClock;
208 }
209
210 const Params *
211 params() const
212 {
213 return dynamic_cast<const Params *>(_params);
214 }
215
216 /*
|
217 * Functions to interact with the interrupt port from IntDev.
218 */
219 Tick read(PacketPtr pkt);
220 Tick write(PacketPtr pkt);
221 Tick recvMessage(PacketPtr pkt);
222 Tick recvResponse(PacketPtr pkt);
223
224 bool
225 triggerTimerInterrupt()
226 {
227 LVTEntry entry = regs[APIC_LVT_TIMER];
228 if (!entry.masked)
229 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
230 return entry.periodic;
231 }
232
233 void addressRanges(AddrRangeList &range_list);
234 void getIntAddrRange(AddrRangeList &range_list);
235
236 Port *getPort(const std::string &if_name, int idx = -1)
237 {
238 if (if_name == "int_port")
239 return intPort;
240 return BasicPioDevice::getPort(if_name, idx);
241 }
242
243 /*
244 * Functions to access and manipulate the APIC's registers.
245 */
246
247 uint32_t readReg(ApicRegIndex miscReg);
248 void setReg(ApicRegIndex reg, uint32_t val);
249 void
250 setRegNoEffect(ApicRegIndex reg, uint32_t val)
251 {
252 regs[reg] = val;
253 }
254
255 /*
256 * Constructor.
257 */
258
259 Interrupts(Params * p);
260
261 /*
262 * Functions for retrieving interrupts for the CPU to handle.
263 */
264
265 bool checkInterrupts(ThreadContext *tc) const;
266 Fault getInterrupt(ThreadContext *tc);
267 void updateIntrInfo(ThreadContext *tc);
268
269 /*
270 * Serialization.
271 */
272
273 void
274 serialize(std::ostream &os)
275 {
276 panic("Interrupts::serialize unimplemented!\n");
277 }
278
279 void
280 unserialize(Checkpoint *cp, const std::string §ion)
281 {
282 panic("Interrupts::unserialize unimplemented!\n");
283 }
284
285 /*
286 * Old functions needed for compatability but which will be phased out
287 * eventually.
288 */
289 void
290 post(int int_num, int index)
291 {
292 panic("Interrupts::post unimplemented!\n");
293 }
294
295 void
296 clear(int int_num, int index)
297 {
298 panic("Interrupts::clear unimplemented!\n");
299 }
300
301 void
302 clearAll()
303 {
304 panic("Interrupts::clearAll unimplemented!\n");
305 }
306};
307
308} // namespace X86ISA
309
310#endif // __ARCH_X86_INTERRUPTS_HH__
| 222 * Functions to interact with the interrupt port from IntDev.
223 */
224 Tick read(PacketPtr pkt);
225 Tick write(PacketPtr pkt);
226 Tick recvMessage(PacketPtr pkt);
227 Tick recvResponse(PacketPtr pkt);
228
229 bool
230 triggerTimerInterrupt()
231 {
232 LVTEntry entry = regs[APIC_LVT_TIMER];
233 if (!entry.masked)
234 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
235 return entry.periodic;
236 }
237
238 void addressRanges(AddrRangeList &range_list);
239 void getIntAddrRange(AddrRangeList &range_list);
240
241 Port *getPort(const std::string &if_name, int idx = -1)
242 {
243 if (if_name == "int_port")
244 return intPort;
245 return BasicPioDevice::getPort(if_name, idx);
246 }
247
248 /*
249 * Functions to access and manipulate the APIC's registers.
250 */
251
252 uint32_t readReg(ApicRegIndex miscReg);
253 void setReg(ApicRegIndex reg, uint32_t val);
254 void
255 setRegNoEffect(ApicRegIndex reg, uint32_t val)
256 {
257 regs[reg] = val;
258 }
259
260 /*
261 * Constructor.
262 */
263
264 Interrupts(Params * p);
265
266 /*
267 * Functions for retrieving interrupts for the CPU to handle.
268 */
269
270 bool checkInterrupts(ThreadContext *tc) const;
271 Fault getInterrupt(ThreadContext *tc);
272 void updateIntrInfo(ThreadContext *tc);
273
274 /*
275 * Serialization.
276 */
277
278 void
279 serialize(std::ostream &os)
280 {
281 panic("Interrupts::serialize unimplemented!\n");
282 }
283
284 void
285 unserialize(Checkpoint *cp, const std::string §ion)
286 {
287 panic("Interrupts::unserialize unimplemented!\n");
288 }
289
290 /*
291 * Old functions needed for compatability but which will be phased out
292 * eventually.
293 */
294 void
295 post(int int_num, int index)
296 {
297 panic("Interrupts::post unimplemented!\n");
298 }
299
300 void
301 clear(int int_num, int index)
302 {
303 panic("Interrupts::clear unimplemented!\n");
304 }
305
306 void
307 clearAll()
308 {
309 panic("Interrupts::clearAll unimplemented!\n");
310 }
311};
312
313} // namespace X86ISA
314
315#endif // __ARCH_X86_INTERRUPTS_HH__
|