1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72
|
73namespace X86ISA
74{
| 73namespace X86ISA {
|
75
76class Interrupts : public BasicPioDevice, IntDev
77{
78 protected:
79 // Storage for the APIC registers
80 uint32_t regs[NUM_APIC_REGS];
81
82 BitUnion32(LVTEntry)
83 Bitfield<7, 0> vector;
84 Bitfield<10, 8> deliveryMode;
85 Bitfield<12> status;
86 Bitfield<13> polarity;
87 Bitfield<14> remoteIRR;
88 Bitfield<15> trigger;
89 Bitfield<16> masked;
90 Bitfield<17> periodic;
91 EndBitUnion(LVTEntry)
92
93 /*
94 * Timing related stuff.
95 */
96 Tick latency;
97 Tick clock;
98
99 class ApicTimerEvent : public Event
100 {
101 private:
102 Interrupts *localApic;
103 public:
104 ApicTimerEvent(Interrupts *_localApic) :
105 Event(), localApic(_localApic)
106 {}
107
108 void process()
109 {
110 assert(localApic);
111 if (localApic->triggerTimerInterrupt()) {
112 localApic->setReg(APIC_INITIAL_COUNT,
113 localApic->readReg(APIC_INITIAL_COUNT));
114 }
115 }
116 };
117
118 ApicTimerEvent apicTimerEvent;
119
120 /*
121 * A set of variables to keep track of interrupts that don't go through
122 * the IRR.
123 */
124 bool pendingSmi;
125 uint8_t smiVector;
126 bool pendingNmi;
127 uint8_t nmiVector;
128 bool pendingExtInt;
129 uint8_t extIntVector;
130 bool pendingInit;
131 uint8_t initVector;
132
133 // This is a quick check whether any of the above (except ExtInt) are set.
134 bool pendingUnmaskableInt;
135
136 /*
137 * IRR and ISR maintenance.
138 */
139 uint8_t IRRV;
140 uint8_t ISRV;
141
142 int
143 findRegArrayMSB(ApicRegIndex base)
144 {
145 int offset = 7;
146 do {
147 if (regs[base + offset] != 0) {
148 return offset * 32 + findMsbSet(regs[base + offset]);
149 }
150 } while (offset--);
151 return 0;
152 }
153
154 void
155 updateIRRV()
156 {
157 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
158 }
159
160 void
161 updateISRV()
162 {
163 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
164 }
165
166 void
167 setRegArrayBit(ApicRegIndex base, uint8_t vector)
168 {
169 regs[base + (vector % 32)] |= (1 << (vector >> 5));
170 }
171
172 void
173 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
174 {
175 regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
176 }
177
178 bool
179 getRegArrayBit(ApicRegIndex base, uint8_t vector)
180 {
181 return bits(regs[base + (vector % 32)], vector >> 5);
182 }
183
184 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
185
186 public:
187 /*
188 * Params stuff.
189 */
190 typedef X86LocalApicParams Params;
191
| 74
75class Interrupts : public BasicPioDevice, IntDev
76{
77 protected:
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
80
81 BitUnion32(LVTEntry)
82 Bitfield<7, 0> vector;
83 Bitfield<10, 8> deliveryMode;
84 Bitfield<12> status;
85 Bitfield<13> polarity;
86 Bitfield<14> remoteIRR;
87 Bitfield<15> trigger;
88 Bitfield<16> masked;
89 Bitfield<17> periodic;
90 EndBitUnion(LVTEntry)
91
92 /*
93 * Timing related stuff.
94 */
95 Tick latency;
96 Tick clock;
97
98 class ApicTimerEvent : public Event
99 {
100 private:
101 Interrupts *localApic;
102 public:
103 ApicTimerEvent(Interrupts *_localApic) :
104 Event(), localApic(_localApic)
105 {}
106
107 void process()
108 {
109 assert(localApic);
110 if (localApic->triggerTimerInterrupt()) {
111 localApic->setReg(APIC_INITIAL_COUNT,
112 localApic->readReg(APIC_INITIAL_COUNT));
113 }
114 }
115 };
116
117 ApicTimerEvent apicTimerEvent;
118
119 /*
120 * A set of variables to keep track of interrupts that don't go through
121 * the IRR.
122 */
123 bool pendingSmi;
124 uint8_t smiVector;
125 bool pendingNmi;
126 uint8_t nmiVector;
127 bool pendingExtInt;
128 uint8_t extIntVector;
129 bool pendingInit;
130 uint8_t initVector;
131
132 // This is a quick check whether any of the above (except ExtInt) are set.
133 bool pendingUnmaskableInt;
134
135 /*
136 * IRR and ISR maintenance.
137 */
138 uint8_t IRRV;
139 uint8_t ISRV;
140
141 int
142 findRegArrayMSB(ApicRegIndex base)
143 {
144 int offset = 7;
145 do {
146 if (regs[base + offset] != 0) {
147 return offset * 32 + findMsbSet(regs[base + offset]);
148 }
149 } while (offset--);
150 return 0;
151 }
152
153 void
154 updateIRRV()
155 {
156 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
157 }
158
159 void
160 updateISRV()
161 {
162 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
163 }
164
165 void
166 setRegArrayBit(ApicRegIndex base, uint8_t vector)
167 {
168 regs[base + (vector % 32)] |= (1 << (vector >> 5));
169 }
170
171 void
172 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
173 {
174 regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
175 }
176
177 bool
178 getRegArrayBit(ApicRegIndex base, uint8_t vector)
179 {
180 return bits(regs[base + (vector % 32)], vector >> 5);
181 }
182
183 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
184
185 public:
186 /*
187 * Params stuff.
188 */
189 typedef X86LocalApicParams Params;
190
|
192 void setClock(Tick newClock)
| 191 void
192 setClock(Tick newClock)
|
193 {
194 clock = newClock;
195 }
196
197 const Params *
198 params() const
199 {
200 return dynamic_cast<const Params *>(_params);
201 }
202
203 /*
204 * Functions to interact with the interrupt port from IntDev.
205 */
206 Tick read(PacketPtr pkt);
207 Tick write(PacketPtr pkt);
208 Tick recvMessage(PacketPtr pkt);
209
210 bool
211 triggerTimerInterrupt()
212 {
213 LVTEntry entry = regs[APIC_LVT_TIMER];
214 if (!entry.masked)
215 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
216 return entry.periodic;
217 }
218
219 void addressRanges(AddrRangeList &range_list)
220 {
221 range_list.clear();
222 range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0),
223 x86LocalAPICAddress(0, 0) + PageBytes));
224 }
225
226 void getIntAddrRange(AddrRangeList &range_list)
227 {
228 range_list.clear();
229 range_list.push_back(RangeEx(x86InterruptAddress(0, 0),
230 x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize));
231 }
232
233 Port *getPort(const std::string &if_name, int idx = -1)
234 {
235 if (if_name == "int_port")
236 return intPort;
237 return BasicPioDevice::getPort(if_name, idx);
238 }
239
240 /*
241 * Functions to access and manipulate the APIC's registers.
242 */
243
244 uint32_t readReg(ApicRegIndex miscReg);
245 void setReg(ApicRegIndex reg, uint32_t val);
| 193 {
194 clock = newClock;
195 }
196
197 const Params *
198 params() const
199 {
200 return dynamic_cast<const Params *>(_params);
201 }
202
203 /*
204 * Functions to interact with the interrupt port from IntDev.
205 */
206 Tick read(PacketPtr pkt);
207 Tick write(PacketPtr pkt);
208 Tick recvMessage(PacketPtr pkt);
209
210 bool
211 triggerTimerInterrupt()
212 {
213 LVTEntry entry = regs[APIC_LVT_TIMER];
214 if (!entry.masked)
215 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
216 return entry.periodic;
217 }
218
219 void addressRanges(AddrRangeList &range_list)
220 {
221 range_list.clear();
222 range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0),
223 x86LocalAPICAddress(0, 0) + PageBytes));
224 }
225
226 void getIntAddrRange(AddrRangeList &range_list)
227 {
228 range_list.clear();
229 range_list.push_back(RangeEx(x86InterruptAddress(0, 0),
230 x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize));
231 }
232
233 Port *getPort(const std::string &if_name, int idx = -1)
234 {
235 if (if_name == "int_port")
236 return intPort;
237 return BasicPioDevice::getPort(if_name, idx);
238 }
239
240 /*
241 * Functions to access and manipulate the APIC's registers.
242 */
243
244 uint32_t readReg(ApicRegIndex miscReg);
245 void setReg(ApicRegIndex reg, uint32_t val);
|
246 void setRegNoEffect(ApicRegIndex reg, uint32_t val)
| 246 void
247 setRegNoEffect(ApicRegIndex reg, uint32_t val)
|
247 {
248 regs[reg] = val;
249 }
250
251 /*
252 * Constructor.
253 */
254
| 248 {
249 regs[reg] = val;
250 }
251
252 /*
253 * Constructor.
254 */
255
|
255 Interrupts(Params * p) : BasicPioDevice(p), IntDev(this),
256 latency(p->pio_latency), clock(0),
257 apicTimerEvent(this),
258 pendingSmi(false), smiVector(0),
259 pendingNmi(false), nmiVector(0),
260 pendingExtInt(false), extIntVector(0),
261 pendingInit(false), initVector(0),
262 pendingUnmaskableInt(false)
| 256 Interrupts(Params * p)
257 : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
258 apicTimerEvent(this),
259 pendingSmi(false), smiVector(0),
260 pendingNmi(false), nmiVector(0),
261 pendingExtInt(false), extIntVector(0),
262 pendingInit(false), initVector(0),
263 pendingUnmaskableInt(false)
|
263 {
264 pioSize = PageBytes;
265 memset(regs, 0, sizeof(regs));
266 //Set the local apic DFR to the flat model.
267 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
268 ISRV = 0;
269 IRRV = 0;
270 }
271
272 /*
273 * Functions for retrieving interrupts for the CPU to handle.
274 */
275
| 264 {
265 pioSize = PageBytes;
266 memset(regs, 0, sizeof(regs));
267 //Set the local apic DFR to the flat model.
268 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
269 ISRV = 0;
270 IRRV = 0;
271 }
272
273 /*
274 * Functions for retrieving interrupts for the CPU to handle.
275 */
276
|
276 bool check_interrupts(ThreadContext * tc) const;
277 Fault getInterrupt(ThreadContext * tc);
278 void updateIntrInfo(ThreadContext * tc);
| 277 bool checkInterrupts(ThreadContext *tc) const;
278 Fault getInterrupt(ThreadContext *tc);
279 void updateIntrInfo(ThreadContext *tc);
|
279
280 /*
281 * Serialization.
282 */
283
| 280
281 /*
282 * Serialization.
283 */
284
|
284 void serialize(std::ostream & os)
| 285 void
286 serialize(std::ostream &os)
|
285 {
286 panic("Interrupts::serialize unimplemented!\n");
287 }
288
| 287 {
288 panic("Interrupts::serialize unimplemented!\n");
289 }
290
|
289 void unserialize(Checkpoint * cp, const std::string & section)
| 291 void
292 unserialize(Checkpoint *cp, const std::string §ion)
|
290 {
291 panic("Interrupts::unserialize unimplemented!\n");
292 }
293
294 /*
295 * Old functions needed for compatability but which will be phased out
296 * eventually.
297 */
| 293 {
294 panic("Interrupts::unserialize unimplemented!\n");
295 }
296
297 /*
298 * Old functions needed for compatability but which will be phased out
299 * eventually.
300 */
|
298 void post(int int_num, int index)
| 301 void
302 post(int int_num, int index)
|
299 {
300 panic("Interrupts::post unimplemented!\n");
301 }
302
| 303 {
304 panic("Interrupts::post unimplemented!\n");
305 }
306
|
303 void clear(int int_num, int index)
| 307 void
308 clear(int int_num, int index)
|
304 {
305 panic("Interrupts::clear unimplemented!\n");
306 }
307
| 309 {
310 panic("Interrupts::clear unimplemented!\n");
311 }
312
|
308 void clear_all()
| 313 void
314 clearAll()
|
309 {
| 315 {
|
310 panic("Interrupts::clear_all unimplemented!\n");
| 316 panic("Interrupts::clearAll unimplemented!\n");
|
311 }
312};
313
| 317 }
318};
319
|
314};
| 320} // namespace X86ISA
|
315
316#endif // __ARCH_X86_INTERRUPTS_HH__
| 321
322#endif // __ARCH_X86_INTERRUPTS_HH__
|