interrupts.cc (9623:327bf4242521) interrupts.cc (9805:a4339e26b429)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 pkt->makeAtomicResponse();
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 208 unchanged lines hidden (view full) ---

217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 pkt->makeAtomicResponse();
225 return latency;
225 return pioDelay;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231 Addr offset = pkt->getAddr() - pioAddr;
232 //Make sure we're at least only accessing one register.
233 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg = decodeAddr(offset);
236 uint32_t val = regs[reg];
237 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238 DPRINTF(LocalApic,
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg, offset, gtoh(val));
241 setReg(reg, gtoh(val));
242 pkt->makeAtomicResponse();
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231 Addr offset = pkt->getAddr() - pioAddr;
232 //Make sure we're at least only accessing one register.
233 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg = decodeAddr(offset);
236 uint32_t val = regs[reg];
237 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238 DPRINTF(LocalApic,
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg, offset, gtoh(val));
241 setReg(reg, gtoh(val));
242 pkt->makeAtomicResponse();
243 return latency;
243 return pioDelay;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247 uint8_t deliveryMode, bool level)
248{
249 /*
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.

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342 }
343 break;
344 default:
345 panic("Local apic got unknown interrupt message at offset %#x.\n",
346 offset);
347 break;
348 }
349 pkt->makeAtomicResponse();
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247 uint8_t deliveryMode, bool level)
248{
249 /*
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.

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342 }
343 break;
344 default:
345 panic("Local apic got unknown interrupt message at offset %#x.\n",
346 offset);
347 break;
348 }
349 pkt->makeAtomicResponse();
350 return latency;
350 return pioDelay;
351}
352
353
354Tick
355X86ISA::Interrupts::recvResponse(PacketPtr pkt)
356{
357 assert(!pkt->isError());
358 assert(pkt->cmd == MemCmd::MessageResp);

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363 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
364 }
365 DPRINTF(LocalApic, "ICR is now idle.\n");
366 return 0;
367}
368
369
370AddrRangeList
351}
352
353
354Tick
355X86ISA::Interrupts::recvResponse(PacketPtr pkt)
356{
357 assert(!pkt->isError());
358 assert(pkt->cmd == MemCmd::MessageResp);

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363 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
364 }
365 DPRINTF(LocalApic, "ICR is now idle.\n");
366 return 0;
367}
368
369
370AddrRangeList
371X86ISA::Interrupts::getAddrRanges() const
372{
373 AddrRangeList ranges;
374 AddrRange range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
375 x86LocalAPICAddress(initialApicId, 0) +
376 PageBytes);
377 ranges.push_back(range);
378 return ranges;
379}
380
381
382AddrRangeList
383X86ISA::Interrupts::getIntAddrRange() const
384{
385 AddrRangeList ranges;
386 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
387 x86InterruptAddress(initialApicId, 0) +
388 PhysAddrAPICRangeSize));
389 return ranges;
390}

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614 break;
615 }
616 regs[reg] = newVal;
617 return;
618}
619
620
621X86ISA::Interrupts::Interrupts(Params * p) :
371X86ISA::Interrupts::getIntAddrRange() const
372{
373 AddrRangeList ranges;
374 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
375 x86InterruptAddress(initialApicId, 0) +
376 PhysAddrAPICRangeSize));
377 return ranges;
378}

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602 break;
603 }
604 regs[reg] = newVal;
605 return;
606}
607
608
609X86ISA::Interrupts::Interrupts(Params * p) :
622 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
610 BasicPioDevice(p), IntDev(this, p->int_latency),
623 apicTimerEvent(this),
624 pendingSmi(false), smiVector(0),
625 pendingNmi(false), nmiVector(0),
626 pendingExtInt(false), extIntVector(0),
627 pendingInit(false), initVector(0),
628 pendingStartup(false), startupVector(0),
629 startedUp(false), pendingUnmaskableInt(false),
630 pendingIPIs(0), cpu(NULL),

--- 164 unchanged lines hidden --- 		611 apicTimerEvent(this),
612 pendingSmi(false), smiVector(0),
613 pendingNmi(false), nmiVector(0),
614 pendingExtInt(false), extIntVector(0),
615 pendingInit(false), initVector(0),
616 pendingStartup(false), startupVector(0),
617 startedUp(false), pendingUnmaskableInt(false),
618 pendingIPIs(0), cpu(NULL),

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