interrupts.cc (6041:949a8304e7f9) interrupts.cc (6046:8ac37d77fa74)
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);

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361 panic("Local APIC Arbitration Priority register unimplemented.\n");
362 break;
363 case APIC_PROCESSOR_PRIORITY:
364 panic("Local APIC Processor Priority register unimplemented.\n");
365 break;
366 case APIC_ERROR_STATUS:
367 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
368 break;
64
65int
66divideFromConf(uint32_t conf)
67{
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);

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362 panic("Local APIC Arbitration Priority register unimplemented.\n");
363 break;
364 case APIC_PROCESSOR_PRIORITY:
365 panic("Local APIC Processor Priority register unimplemented.\n");
366 break;
367 case APIC_ERROR_STATUS:
368 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
369 break;
369 case APIC_INTERRUPT_COMMAND_LOW:
370 panic("Local APIC Interrupt Command low"
371 " register unimplemented.\n");
372 break;
373 case APIC_INTERRUPT_COMMAND_HIGH:
374 panic("Local APIC Interrupt Command high"
375 " register unimplemented.\n");
376 break;
377 case APIC_CURRENT_COUNT:
378 {
379 if (apicTimerEvent.scheduled()) {
380 assert(clock);
381 // Compute how many m5 ticks happen per count.
382 uint64_t ticksPerCount = clock *
383 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
384 // Compute how many m5 ticks are left.

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454 } else {
455 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
456 return;
457 }
458
459 }
460 break;
461 case APIC_INTERRUPT_COMMAND_LOW:
370 case APIC_CURRENT_COUNT:
371 {
372 if (apicTimerEvent.scheduled()) {
373 assert(clock);
374 // Compute how many m5 ticks happen per count.
375 uint64_t ticksPerCount = clock *
376 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
377 // Compute how many m5 ticks are left.

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447 } else {
448 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
449 return;
450 }
451
452 }
453 break;
454 case APIC_INTERRUPT_COMMAND_LOW:
462 panic("Local APIC Interrupt Command low"
463 " register unimplemented.\n");
455 {
456 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
457 // Check if we're already sending an IPI.
458 if (low.deliveryStatus) {
459 newVal = low;
460 break;
461 }
462 low = val;
463 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
464 // Record that an IPI is being sent.
465 low.deliveryStatus = 1;
466 TriggerIntMessage message;
467 message.destination = high.destination;
468 message.vector = low.vector;
469 message.deliveryMode = low.deliveryMode;
470 message.destMode = low.destMode;
471 message.level = low.level;
472 message.trigger = low.trigger;
473 bool timing = sys->getMemoryMode() == Enums::timing;
474 switch (low.destShorthand) {
475 case 0:
476 intPort->sendMessage(message, timing);
477 break;
478 case 1:
479 panic("Self IPIs aren't implemented.\n");
480 break;
481 case 2:
482 panic("Broadcast including self IPIs aren't implemented.\n");
483 break;
484 case 3:
485 panic("Broadcast excluding self IPIs aren't implemented.\n");
486 break;
487 }
488 }
464 break;
489 break;
465 case APIC_INTERRUPT_COMMAND_HIGH:
466 panic("Local APIC Interrupt Command high"
467 " register unimplemented.\n");
468 break;
469 case APIC_LVT_TIMER:
470 case APIC_LVT_THERMAL_SENSOR:
471 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
472 case APIC_LVT_LINT0:
473 case APIC_LVT_LINT1:
474 case APIC_LVT_ERROR:
475 {
476 uint64_t readOnlyMask = (1 << 12) | (1 << 14);

--- 142 unchanged lines hidden --- 		490 case APIC_LVT_TIMER:
491 case APIC_LVT_THERMAL_SENSOR:
492 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
493 case APIC_LVT_LINT0:
494 case APIC_LVT_LINT1:
495 case APIC_LVT_ERROR:
496 {
497 uint64_t readOnlyMask = (1 << 12) | (1 << 14);

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