interrupts.cc (5848:441f446c76f6) interrupts.cc (5898:541097c69e22)
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 207 unchanged lines hidden (view full) ---

216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 pkt->makeAtomicResponse();
224 return latency;
225}
226
227Tick
228X86ISA::Interrupts::write(PacketPtr pkt)
229{
230 Addr offset = pkt->getAddr() - pioAddr;
231 //Make sure we're at least only accessing one register.
232 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
233 panic("Accessed more than one register at a time in the APIC!\n");
234 ApicRegIndex reg = decodeAddr(offset);
235 uint32_t val = regs[reg];
236 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
237 DPRINTF(LocalApic,
238 "Writing Local APIC register %d at offset %#x as %#x.\n",
239 reg, offset, gtoh(val));
240 setReg(reg, gtoh(val));
225 return latency;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231 Addr offset = pkt->getAddr() - pioAddr;
232 //Make sure we're at least only accessing one register.
233 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg = decodeAddr(offset);
236 uint32_t val = regs[reg];
237 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238 DPRINTF(LocalApic,
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg, offset, gtoh(val));
241 setReg(reg, gtoh(val));
242 pkt->makeAtomicResponse();
241 return latency;
242}
243void
244X86ISA::Interrupts::requestInterrupt(uint8_t vector,
245 uint8_t deliveryMode, bool level)
246{
247 /*
248 * Fixed and lowest-priority delivery mode interrupts are handled

--- 319 unchanged lines hidden --- 		243 return latency;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247 uint8_t deliveryMode, bool level)
248{
249 /*
250 * Fixed and lowest-priority delivery mode interrupts are handled

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