interrupts.cc (5811:219a39f70082) interrupts.cc (5848:441f446c76f6)
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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339 " register unimplemented.\n");
340 break;
341 case APIC_INTERRUPT_COMMAND_HIGH:
342 panic("Local APIC Interrupt Command high"
343 " register unimplemented.\n");
344 break;
345 case APIC_CURRENT_COUNT:
346 {
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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339 " register unimplemented.\n");
340 break;
341 case APIC_INTERRUPT_COMMAND_HIGH:
342 panic("Local APIC Interrupt Command high"
343 " register unimplemented.\n");
344 break;
345 case APIC_CURRENT_COUNT:
346 {
347 assert(clock);
348 uint32_t val = regs[reg] - curTick / clock;
349 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
350 return val;
347 if (apicTimerEvent.scheduled()) {
348 assert(clock);
349 // Compute how many m5 ticks happen per count.
350 uint64_t ticksPerCount = clock *
351 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
352 // Compute how many m5 ticks are left.
353 uint64_t val = apicTimerEvent.when() - curTick;
354 // Turn that into a count.
355 val = (val + ticksPerCount - 1) / ticksPerCount;
356 return val;
357 } else {
358 return 0;
359 }
351 }
352 default:
353 break;
354 }
355 return regs[reg];
356}
357
358void

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436 newVal = (val & ~readOnlyMask) |
437 (regs[reg] & readOnlyMask);
438 }
439 break;
440 case APIC_INITIAL_COUNT:
441 {
442 assert(clock);
443 newVal = bits(val, 31, 0);
360 }
361 default:
362 break;
363 }
364 return regs[reg];
365}
366
367void

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445 newVal = (val & ~readOnlyMask) |
446 (regs[reg] & readOnlyMask);
447 }
448 break;
449 case APIC_INITIAL_COUNT:
450 {
451 assert(clock);
452 newVal = bits(val, 31, 0);
444 uint32_t newCount = newVal *
445 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
446 regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
447 // Find out how long a "tick" of the timer should take.
448 Tick timerTick = 16 * clock;
453 // Compute how many timer ticks we're being programmed for.
454 uint64_t newCount = newVal *
455 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
449 // Schedule on the edge of the next tick plus the new count.
456 // Schedule on the edge of the next tick plus the new count.
450 Tick offset = curTick % timerTick;
457 Tick offset = curTick % clock;
451 if (offset) {
452 reschedule(apicTimerEvent,
458 if (offset) {
459 reschedule(apicTimerEvent,
453 curTick + (newCount + 1) * timerTick - offset, true);
460 curTick + (newCount + 1) * clock - offset, true);
454 } else {
455 reschedule(apicTimerEvent,
461 } else {
462 reschedule(apicTimerEvent,
456 curTick + newCount * timerTick, true);
463 curTick + newCount * clock, true);
457 }
458 }
459 break;
460 case APIC_CURRENT_COUNT:
461 //Local APIC Current Count register is read only.
462 return;
463 case APIC_DIVIDE_CONFIGURATION:
464 newVal = val & 0xB;

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465 }
466 break;
467 case APIC_CURRENT_COUNT:
468 //Local APIC Current Count register is read only.
469 return;
470 case APIC_DIVIDE_CONFIGURATION:
471 newVal = val & 0xB;

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