1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/regs/apic.hh"
41#include "arch/x86/interrupts.hh"
42#include "arch/x86/intmessage.hh"
43#include "cpu/base.hh"
44#include "debug/LocalApic.hh"
45#include "dev/x86/i82094aa.hh"
46#include "dev/x86/pc.hh"
47#include "dev/x86/south_bridge.hh"
48#include "mem/packet_access.hh"
49#include "sim/system.hh"
50#include "sim/full_system.hh"
51
52int
53divideFromConf(uint32_t conf)
54{
55 // This figures out what division we want from the division configuration
56 // register in the local APIC. The encoding is a little odd but it can
57 // be deciphered fairly easily.
58 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
59 shift = (shift + 1) % 8;
60 return 1 << shift;
61}
62
63namespace X86ISA
64{
65
66ApicRegIndex
67decodeAddr(Addr paddr)
68{
69 ApicRegIndex regNum;
70 paddr &= ~mask(3);
71 switch (paddr)
72 {
73 case 0x20:
74 regNum = APIC_ID;
75 break;
76 case 0x30:
77 regNum = APIC_VERSION;
78 break;
79 case 0x80:
80 regNum = APIC_TASK_PRIORITY;
81 break;
82 case 0x90:
83 regNum = APIC_ARBITRATION_PRIORITY;
84 break;
85 case 0xA0:
86 regNum = APIC_PROCESSOR_PRIORITY;
87 break;
88 case 0xB0:
89 regNum = APIC_EOI;
90 break;
91 case 0xD0:
92 regNum = APIC_LOGICAL_DESTINATION;
93 break;
94 case 0xE0:
95 regNum = APIC_DESTINATION_FORMAT;
96 break;
97 case 0xF0:
98 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
99 break;
100 case 0x100:
101 case 0x108:
102 case 0x110:
103 case 0x118:
104 case 0x120:
105 case 0x128:
106 case 0x130:
107 case 0x138:
108 case 0x140:
109 case 0x148:
110 case 0x150:
111 case 0x158:
112 case 0x160:
113 case 0x168:
114 case 0x170:
115 case 0x178:
116 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
117 break;
118 case 0x180:
119 case 0x188:
120 case 0x190:
121 case 0x198:
122 case 0x1A0:
123 case 0x1A8:
124 case 0x1B0:
125 case 0x1B8:
126 case 0x1C0:
127 case 0x1C8:
128 case 0x1D0:
129 case 0x1D8:
130 case 0x1E0:
131 case 0x1E8:
132 case 0x1F0:
133 case 0x1F8:
134 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
135 break;
136 case 0x200:
137 case 0x208:
138 case 0x210:
139 case 0x218:
140 case 0x220:
141 case 0x228:
142 case 0x230:
143 case 0x238:
144 case 0x240:
145 case 0x248:
146 case 0x250:
147 case 0x258:
148 case 0x260:
149 case 0x268:
150 case 0x270:
151 case 0x278:
152 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
153 break;
154 case 0x280:
155 regNum = APIC_ERROR_STATUS;
156 break;
157 case 0x300:
158 regNum = APIC_INTERRUPT_COMMAND_LOW;
159 break;
160 case 0x310:
161 regNum = APIC_INTERRUPT_COMMAND_HIGH;
162 break;
163 case 0x320:
164 regNum = APIC_LVT_TIMER;
165 break;
166 case 0x330:
167 regNum = APIC_LVT_THERMAL_SENSOR;
168 break;
169 case 0x340:
170 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
171 break;
172 case 0x350:
173 regNum = APIC_LVT_LINT0;
174 break;
175 case 0x360:
176 regNum = APIC_LVT_LINT1;
177 break;
178 case 0x370:
179 regNum = APIC_LVT_ERROR;
180 break;
181 case 0x380:
182 regNum = APIC_INITIAL_COUNT;
183 break;
184 case 0x390:
185 regNum = APIC_CURRENT_COUNT;
186 break;
187 case 0x3E0:
188 regNum = APIC_DIVIDE_CONFIGURATION;
189 break;
190 default:
191 // A reserved register field.
192 panic("Accessed reserved register field %#x.\n", paddr);
193 break;
194 }
195 return regNum;
196}
197}
198
199Tick
200X86ISA::Interrupts::read(PacketPtr pkt)
201{
202 Addr offset = pkt->getAddr() - pioAddr;
203 //Make sure we're at least only accessing one register.
204 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
205 panic("Accessed more than one register at a time in the APIC!\n");
206 ApicRegIndex reg = decodeAddr(offset);
207 uint32_t val = htog(readReg(reg));
208 DPRINTF(LocalApic,
209 "Reading Local APIC register %d at offset %#x as %#x.\n",
210 reg, offset, val);
211 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
212 pkt->makeAtomicResponse();
213 return latency;
214}
215
216Tick
217X86ISA::Interrupts::write(PacketPtr pkt)
218{
219 Addr offset = pkt->getAddr() - pioAddr;
220 //Make sure we're at least only accessing one register.
221 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
222 panic("Accessed more than one register at a time in the APIC!\n");
223 ApicRegIndex reg = decodeAddr(offset);
224 uint32_t val = regs[reg];
225 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
226 DPRINTF(LocalApic,
227 "Writing Local APIC register %d at offset %#x as %#x.\n",
228 reg, offset, gtoh(val));
229 setReg(reg, gtoh(val));
230 pkt->makeAtomicResponse();
231 return latency;
232}
233void
234X86ISA::Interrupts::requestInterrupt(uint8_t vector,
235 uint8_t deliveryMode, bool level)
236{
237 /*
238 * Fixed and lowest-priority delivery mode interrupts are handled
239 * using the IRR/ISR registers, checking against the TPR, etc.
240 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
241 */
242 if (deliveryMode == DeliveryMode::Fixed ||
243 deliveryMode == DeliveryMode::LowestPriority) {
244 DPRINTF(LocalApic, "Interrupt is an %s.\n",
245 DeliveryMode::names[deliveryMode]);
246 // Queue up the interrupt in the IRR.
247 if (vector > IRRV)
248 IRRV = vector;
249 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
250 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
251 if (level) {
252 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253 } else {
254 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
255 }
256 }
257 } else if (!DeliveryMode::isReserved(deliveryMode)) {
258 DPRINTF(LocalApic, "Interrupt is an %s.\n",
259 DeliveryMode::names[deliveryMode]);
260 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
261 pendingUnmaskableInt = pendingSmi = true;
262 smiVector = vector;
263 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
264 pendingUnmaskableInt = pendingNmi = true;
265 nmiVector = vector;
266 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
267 pendingExtInt = true;
268 extIntVector = vector;
269 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
270 pendingUnmaskableInt = pendingInit = true;
271 initVector = vector;
272 } else if (deliveryMode == DeliveryMode::SIPI &&
273 !pendingStartup && !startedUp) {
274 pendingUnmaskableInt = pendingStartup = true;
275 startupVector = vector;
276 }
277 }
278 if (FullSystem)
279 cpu->wakeup();
280}
281
282
283void
284X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
285{
286 assert(newCPU);
287 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
288 panic("Local APICs can't be moved between CPUs"
289 " with different IDs.\n");
290 }
291 cpu = newCPU;
292 initialApicId = cpu->cpuId();
293 regs[APIC_ID] = (initialApicId << 24);
294}
295
296
297void
298X86ISA::Interrupts::init()
299{
300 //
301 // The local apic must register its address ranges on both its pio port
302 // via the basicpiodevice(piodevice) init() function and its int port
303 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
304 //
305 BasicPioDevice::init();
306 IntDev::init();
307}
308
309
310Tick
311X86ISA::Interrupts::recvMessage(PacketPtr pkt)
312{
313 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
314 assert(pkt->cmd == MemCmd::MessageReq);
315 switch(offset)
316 {
317 case 0:
318 {
319 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
320 DPRINTF(LocalApic,
321 "Got Trigger Interrupt message with vector %#x.\n",
322 message.vector);
323
324 requestInterrupt(message.vector,
325 message.deliveryMode, message.trigger);
326 }
327 break;
328 default:
329 panic("Local apic got unknown interrupt message at offset %#x.\n",
330 offset);
331 break;
332 }
333 pkt->makeAtomicResponse();
334 return latency;
335}
336
337
338Tick
339X86ISA::Interrupts::recvResponse(PacketPtr pkt)
340{
341 assert(!pkt->isError());
342 assert(pkt->cmd == MemCmd::MessageResp);
343 if (--pendingIPIs == 0) {
344 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
345 // Record that the ICR is now idle.
346 low.deliveryStatus = 0;
347 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
348 }
349 DPRINTF(LocalApic, "ICR is now idle.\n");
350 return 0;
351}
352
353
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/regs/apic.hh"
41#include "arch/x86/interrupts.hh"
42#include "arch/x86/intmessage.hh"
43#include "cpu/base.hh"
44#include "debug/LocalApic.hh"
45#include "dev/x86/i82094aa.hh"
46#include "dev/x86/pc.hh"
47#include "dev/x86/south_bridge.hh"
48#include "mem/packet_access.hh"
49#include "sim/system.hh"
50#include "sim/full_system.hh"
51
52int
53divideFromConf(uint32_t conf)
54{
55 // This figures out what division we want from the division configuration
56 // register in the local APIC. The encoding is a little odd but it can
57 // be deciphered fairly easily.
58 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
59 shift = (shift + 1) % 8;
60 return 1 << shift;
61}
62
63namespace X86ISA
64{
65
66ApicRegIndex
67decodeAddr(Addr paddr)
68{
69 ApicRegIndex regNum;
70 paddr &= ~mask(3);
71 switch (paddr)
72 {
73 case 0x20:
74 regNum = APIC_ID;
75 break;
76 case 0x30:
77 regNum = APIC_VERSION;
78 break;
79 case 0x80:
80 regNum = APIC_TASK_PRIORITY;
81 break;
82 case 0x90:
83 regNum = APIC_ARBITRATION_PRIORITY;
84 break;
85 case 0xA0:
86 regNum = APIC_PROCESSOR_PRIORITY;
87 break;
88 case 0xB0:
89 regNum = APIC_EOI;
90 break;
91 case 0xD0:
92 regNum = APIC_LOGICAL_DESTINATION;
93 break;
94 case 0xE0:
95 regNum = APIC_DESTINATION_FORMAT;
96 break;
97 case 0xF0:
98 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
99 break;
100 case 0x100:
101 case 0x108:
102 case 0x110:
103 case 0x118:
104 case 0x120:
105 case 0x128:
106 case 0x130:
107 case 0x138:
108 case 0x140:
109 case 0x148:
110 case 0x150:
111 case 0x158:
112 case 0x160:
113 case 0x168:
114 case 0x170:
115 case 0x178:
116 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
117 break;
118 case 0x180:
119 case 0x188:
120 case 0x190:
121 case 0x198:
122 case 0x1A0:
123 case 0x1A8:
124 case 0x1B0:
125 case 0x1B8:
126 case 0x1C0:
127 case 0x1C8:
128 case 0x1D0:
129 case 0x1D8:
130 case 0x1E0:
131 case 0x1E8:
132 case 0x1F0:
133 case 0x1F8:
134 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
135 break;
136 case 0x200:
137 case 0x208:
138 case 0x210:
139 case 0x218:
140 case 0x220:
141 case 0x228:
142 case 0x230:
143 case 0x238:
144 case 0x240:
145 case 0x248:
146 case 0x250:
147 case 0x258:
148 case 0x260:
149 case 0x268:
150 case 0x270:
151 case 0x278:
152 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
153 break;
154 case 0x280:
155 regNum = APIC_ERROR_STATUS;
156 break;
157 case 0x300:
158 regNum = APIC_INTERRUPT_COMMAND_LOW;
159 break;
160 case 0x310:
161 regNum = APIC_INTERRUPT_COMMAND_HIGH;
162 break;
163 case 0x320:
164 regNum = APIC_LVT_TIMER;
165 break;
166 case 0x330:
167 regNum = APIC_LVT_THERMAL_SENSOR;
168 break;
169 case 0x340:
170 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
171 break;
172 case 0x350:
173 regNum = APIC_LVT_LINT0;
174 break;
175 case 0x360:
176 regNum = APIC_LVT_LINT1;
177 break;
178 case 0x370:
179 regNum = APIC_LVT_ERROR;
180 break;
181 case 0x380:
182 regNum = APIC_INITIAL_COUNT;
183 break;
184 case 0x390:
185 regNum = APIC_CURRENT_COUNT;
186 break;
187 case 0x3E0:
188 regNum = APIC_DIVIDE_CONFIGURATION;
189 break;
190 default:
191 // A reserved register field.
192 panic("Accessed reserved register field %#x.\n", paddr);
193 break;
194 }
195 return regNum;
196}
197}
198
199Tick
200X86ISA::Interrupts::read(PacketPtr pkt)
201{
202 Addr offset = pkt->getAddr() - pioAddr;
203 //Make sure we're at least only accessing one register.
204 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
205 panic("Accessed more than one register at a time in the APIC!\n");
206 ApicRegIndex reg = decodeAddr(offset);
207 uint32_t val = htog(readReg(reg));
208 DPRINTF(LocalApic,
209 "Reading Local APIC register %d at offset %#x as %#x.\n",
210 reg, offset, val);
211 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
212 pkt->makeAtomicResponse();
213 return latency;
214}
215
216Tick
217X86ISA::Interrupts::write(PacketPtr pkt)
218{
219 Addr offset = pkt->getAddr() - pioAddr;
220 //Make sure we're at least only accessing one register.
221 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
222 panic("Accessed more than one register at a time in the APIC!\n");
223 ApicRegIndex reg = decodeAddr(offset);
224 uint32_t val = regs[reg];
225 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
226 DPRINTF(LocalApic,
227 "Writing Local APIC register %d at offset %#x as %#x.\n",
228 reg, offset, gtoh(val));
229 setReg(reg, gtoh(val));
230 pkt->makeAtomicResponse();
231 return latency;
232}
233void
234X86ISA::Interrupts::requestInterrupt(uint8_t vector,
235 uint8_t deliveryMode, bool level)
236{
237 /*
238 * Fixed and lowest-priority delivery mode interrupts are handled
239 * using the IRR/ISR registers, checking against the TPR, etc.
240 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
241 */
242 if (deliveryMode == DeliveryMode::Fixed ||
243 deliveryMode == DeliveryMode::LowestPriority) {
244 DPRINTF(LocalApic, "Interrupt is an %s.\n",
245 DeliveryMode::names[deliveryMode]);
246 // Queue up the interrupt in the IRR.
247 if (vector > IRRV)
248 IRRV = vector;
249 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
250 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
251 if (level) {
252 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253 } else {
254 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
255 }
256 }
257 } else if (!DeliveryMode::isReserved(deliveryMode)) {
258 DPRINTF(LocalApic, "Interrupt is an %s.\n",
259 DeliveryMode::names[deliveryMode]);
260 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
261 pendingUnmaskableInt = pendingSmi = true;
262 smiVector = vector;
263 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
264 pendingUnmaskableInt = pendingNmi = true;
265 nmiVector = vector;
266 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
267 pendingExtInt = true;
268 extIntVector = vector;
269 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
270 pendingUnmaskableInt = pendingInit = true;
271 initVector = vector;
272 } else if (deliveryMode == DeliveryMode::SIPI &&
273 !pendingStartup && !startedUp) {
274 pendingUnmaskableInt = pendingStartup = true;
275 startupVector = vector;
276 }
277 }
278 if (FullSystem)
279 cpu->wakeup();
280}
281
282
283void
284X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
285{
286 assert(newCPU);
287 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
288 panic("Local APICs can't be moved between CPUs"
289 " with different IDs.\n");
290 }
291 cpu = newCPU;
292 initialApicId = cpu->cpuId();
293 regs[APIC_ID] = (initialApicId << 24);
294}
295
296
297void
298X86ISA::Interrupts::init()
299{
300 //
301 // The local apic must register its address ranges on both its pio port
302 // via the basicpiodevice(piodevice) init() function and its int port
303 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
304 //
305 BasicPioDevice::init();
306 IntDev::init();
307}
308
309
310Tick
311X86ISA::Interrupts::recvMessage(PacketPtr pkt)
312{
313 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
314 assert(pkt->cmd == MemCmd::MessageReq);
315 switch(offset)
316 {
317 case 0:
318 {
319 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
320 DPRINTF(LocalApic,
321 "Got Trigger Interrupt message with vector %#x.\n",
322 message.vector);
323
324 requestInterrupt(message.vector,
325 message.deliveryMode, message.trigger);
326 }
327 break;
328 default:
329 panic("Local apic got unknown interrupt message at offset %#x.\n",
330 offset);
331 break;
332 }
333 pkt->makeAtomicResponse();
334 return latency;
335}
336
337
338Tick
339X86ISA::Interrupts::recvResponse(PacketPtr pkt)
340{
341 assert(!pkt->isError());
342 assert(pkt->cmd == MemCmd::MessageResp);
343 if (--pendingIPIs == 0) {
344 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
345 // Record that the ICR is now idle.
346 low.deliveryStatus = 0;
347 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
348 }
349 DPRINTF(LocalApic, "ICR is now idle.\n");
350 return 0;
351}
352
353
|
354void
355X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
| 354AddrRangeList
355X86ISA::Interrupts::getAddrRanges()
|
356{
| 356{
|
357 range_list.clear();
| 357 AddrRangeList ranges;
|
358 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
359 x86LocalAPICAddress(initialApicId, 0) +
360 PageBytes);
| 358 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
359 x86LocalAPICAddress(initialApicId, 0) +
360 PageBytes);
|
361 range_list.push_back(range);
| 361 ranges.push_back(range);
|
362 pioAddr = range.start;
| 362 pioAddr = range.start;
|
| 363 return ranges;
|
363}
364
365
| 364}
365
366
|
366void
367X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
| 367AddrRangeList
368X86ISA::Interrupts::getIntAddrRange()
|
368{
| 369{
|
369 range_list.clear();
370 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
371 x86InterruptAddress(initialApicId, 0) +
372 PhysAddrAPICRangeSize));
| 370 AddrRangeList ranges;
371 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
372 x86InterruptAddress(initialApicId, 0) +
373 PhysAddrAPICRangeSize));
374 return ranges;
|
373}
374
375
376uint32_t
377X86ISA::Interrupts::readReg(ApicRegIndex reg)
378{
379 if (reg >= APIC_TRIGGER_MODE(0) &&
380 reg <= APIC_TRIGGER_MODE(15)) {
381 panic("Local APIC Trigger Mode registers are unimplemented.\n");
382 }
383 switch (reg) {
384 case APIC_ARBITRATION_PRIORITY:
385 panic("Local APIC Arbitration Priority register unimplemented.\n");
386 break;
387 case APIC_PROCESSOR_PRIORITY:
388 panic("Local APIC Processor Priority register unimplemented.\n");
389 break;
390 case APIC_ERROR_STATUS:
391 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
392 break;
393 case APIC_CURRENT_COUNT:
394 {
395 if (apicTimerEvent.scheduled()) {
396 assert(clock);
397 // Compute how many m5 ticks happen per count.
398 uint64_t ticksPerCount = clock *
399 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
400 // Compute how many m5 ticks are left.
401 uint64_t val = apicTimerEvent.when() - curTick();
402 // Turn that into a count.
403 val = (val + ticksPerCount - 1) / ticksPerCount;
404 return val;
405 } else {
406 return 0;
407 }
408 }
409 default:
410 break;
411 }
412 return regs[reg];
413}
414
415void
416X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
417{
418 uint32_t newVal = val;
419 if (reg >= APIC_IN_SERVICE(0) &&
420 reg <= APIC_IN_SERVICE(15)) {
421 panic("Local APIC In-Service registers are unimplemented.\n");
422 }
423 if (reg >= APIC_TRIGGER_MODE(0) &&
424 reg <= APIC_TRIGGER_MODE(15)) {
425 panic("Local APIC Trigger Mode registers are unimplemented.\n");
426 }
427 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
428 reg <= APIC_INTERRUPT_REQUEST(15)) {
429 panic("Local APIC Interrupt Request registers "
430 "are unimplemented.\n");
431 }
432 switch (reg) {
433 case APIC_ID:
434 newVal = val & 0xFF;
435 break;
436 case APIC_VERSION:
437 // The Local APIC Version register is read only.
438 return;
439 case APIC_TASK_PRIORITY:
440 newVal = val & 0xFF;
441 break;
442 case APIC_ARBITRATION_PRIORITY:
443 panic("Local APIC Arbitration Priority register unimplemented.\n");
444 break;
445 case APIC_PROCESSOR_PRIORITY:
446 panic("Local APIC Processor Priority register unimplemented.\n");
447 break;
448 case APIC_EOI:
449 // Remove the interrupt that just completed from the local apic state.
450 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
451 updateISRV();
452 return;
453 case APIC_LOGICAL_DESTINATION:
454 newVal = val & 0xFF000000;
455 break;
456 case APIC_DESTINATION_FORMAT:
457 newVal = val | 0x0FFFFFFF;
458 break;
459 case APIC_SPURIOUS_INTERRUPT_VECTOR:
460 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
461 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
462 if (val & (1 << 9))
463 warn("Focus processor checking not implemented.\n");
464 break;
465 case APIC_ERROR_STATUS:
466 {
467 if (regs[APIC_INTERNAL_STATE] & 0x1) {
468 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
469 newVal = 0;
470 } else {
471 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
472 return;
473 }
474
475 }
476 break;
477 case APIC_INTERRUPT_COMMAND_LOW:
478 {
479 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
480 // Check if we're already sending an IPI.
481 if (low.deliveryStatus) {
482 newVal = low;
483 break;
484 }
485 low = val;
486 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
487 // Record that an IPI is being sent.
488 low.deliveryStatus = 1;
489 TriggerIntMessage message = 0;
490 message.destination = high.destination;
491 message.vector = low.vector;
492 message.deliveryMode = low.deliveryMode;
493 message.destMode = low.destMode;
494 message.level = low.level;
495 message.trigger = low.trigger;
496 bool timing = sys->getMemoryMode() == Enums::timing;
497 // Be careful no updates of the delivery status bit get lost.
498 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
499 ApicList apics;
500 int numContexts = sys->numContexts();
501 switch (low.destShorthand) {
502 case 0:
503 if (message.deliveryMode == DeliveryMode::LowestPriority) {
504 panic("Lowest priority delivery mode "
505 "IPIs aren't implemented.\n");
506 }
507 if (message.destMode == 1) {
508 int dest = message.destination;
509 hack_once("Assuming logical destinations are 1 << id.\n");
510 for (int i = 0; i < numContexts; i++) {
511 if (dest & 0x1)
512 apics.push_back(i);
513 dest = dest >> 1;
514 }
515 } else {
516 if (message.destination == 0xFF) {
517 for (int i = 0; i < numContexts; i++) {
518 if (i == initialApicId) {
519 requestInterrupt(message.vector,
520 message.deliveryMode, message.trigger);
521 } else {
522 apics.push_back(i);
523 }
524 }
525 } else {
526 if (message.destination == initialApicId) {
527 requestInterrupt(message.vector,
528 message.deliveryMode, message.trigger);
529 } else {
530 apics.push_back(message.destination);
531 }
532 }
533 }
534 break;
535 case 1:
536 newVal = val;
537 requestInterrupt(message.vector,
538 message.deliveryMode, message.trigger);
539 break;
540 case 2:
541 requestInterrupt(message.vector,
542 message.deliveryMode, message.trigger);
543 // Fall through
544 case 3:
545 {
546 for (int i = 0; i < numContexts; i++) {
547 if (i != initialApicId) {
548 apics.push_back(i);
549 }
550 }
551 }
552 break;
553 }
554 pendingIPIs += apics.size();
555 intPort->sendMessage(apics, message, timing);
556 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
557 }
558 break;
559 case APIC_LVT_TIMER:
560 case APIC_LVT_THERMAL_SENSOR:
561 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
562 case APIC_LVT_LINT0:
563 case APIC_LVT_LINT1:
564 case APIC_LVT_ERROR:
565 {
566 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
567 newVal = (val & ~readOnlyMask) |
568 (regs[reg] & readOnlyMask);
569 }
570 break;
571 case APIC_INITIAL_COUNT:
572 {
573 assert(clock);
574 newVal = bits(val, 31, 0);
575 // Compute how many timer ticks we're being programmed for.
576 uint64_t newCount = newVal *
577 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
578 // Schedule on the edge of the next tick plus the new count.
579 Tick offset = curTick() % clock;
580 if (offset) {
581 reschedule(apicTimerEvent,
582 curTick() + (newCount + 1) * clock - offset, true);
583 } else {
584 reschedule(apicTimerEvent,
585 curTick() + newCount * clock, true);
586 }
587 }
588 break;
589 case APIC_CURRENT_COUNT:
590 //Local APIC Current Count register is read only.
591 return;
592 case APIC_DIVIDE_CONFIGURATION:
593 newVal = val & 0xB;
594 break;
595 default:
596 break;
597 }
598 regs[reg] = newVal;
599 return;
600}
601
602
603X86ISA::Interrupts::Interrupts(Params * p) :
604 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
605 clock(0),
606 apicTimerEvent(this),
607 pendingSmi(false), smiVector(0),
608 pendingNmi(false), nmiVector(0),
609 pendingExtInt(false), extIntVector(0),
610 pendingInit(false), initVector(0),
611 pendingStartup(false), startupVector(0),
612 startedUp(false), pendingUnmaskableInt(false),
613 pendingIPIs(0), cpu(NULL)
614{
615 pioSize = PageBytes;
616 memset(regs, 0, sizeof(regs));
617 //Set the local apic DFR to the flat model.
618 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
619 ISRV = 0;
620 IRRV = 0;
621}
622
623
624bool
625X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
626{
627 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
628 if (pendingUnmaskableInt) {
629 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
630 return true;
631 }
632 if (rflags.intf) {
633 if (pendingExtInt) {
634 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
635 return true;
636 }
637 if (IRRV > ISRV && bits(IRRV, 7, 4) >
638 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
639 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
640 return true;
641 }
642 }
643 return false;
644}
645
646Fault
647X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
648{
649 assert(checkInterrupts(tc));
650 // These are all probably fairly uncommon, so we'll make them easier to
651 // check for.
652 if (pendingUnmaskableInt) {
653 if (pendingSmi) {
654 DPRINTF(LocalApic, "Generated SMI fault object.\n");
655 return new SystemManagementInterrupt();
656 } else if (pendingNmi) {
657 DPRINTF(LocalApic, "Generated NMI fault object.\n");
658 return new NonMaskableInterrupt(nmiVector);
659 } else if (pendingInit) {
660 DPRINTF(LocalApic, "Generated INIT fault object.\n");
661 return new InitInterrupt(initVector);
662 } else if (pendingStartup) {
663 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
664 return new StartupInterrupt(startupVector);
665 } else {
666 panic("pendingUnmaskableInt set, but no unmaskable "
667 "ints were pending.\n");
668 return NoFault;
669 }
670 } else if (pendingExtInt) {
671 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
672 return new ExternalInterrupt(extIntVector);
673 } else {
674 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
675 // The only thing left are fixed and lowest priority interrupts.
676 return new ExternalInterrupt(IRRV);
677 }
678}
679
680void
681X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
682{
683 assert(checkInterrupts(tc));
684 if (pendingUnmaskableInt) {
685 if (pendingSmi) {
686 DPRINTF(LocalApic, "SMI sent to core.\n");
687 pendingSmi = false;
688 } else if (pendingNmi) {
689 DPRINTF(LocalApic, "NMI sent to core.\n");
690 pendingNmi = false;
691 } else if (pendingInit) {
692 DPRINTF(LocalApic, "Init sent to core.\n");
693 pendingInit = false;
694 startedUp = false;
695 } else if (pendingStartup) {
696 DPRINTF(LocalApic, "SIPI sent to core.\n");
697 pendingStartup = false;
698 startedUp = true;
699 }
700 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
701 pendingUnmaskableInt = false;
702 } else if (pendingExtInt) {
703 pendingExtInt = false;
704 } else {
705 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
706 // Mark the interrupt as "in service".
707 ISRV = IRRV;
708 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
709 // Clear it out of the IRR.
710 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
711 updateIRRV();
712 }
713}
714
715void
716X86ISA::Interrupts::serialize(std::ostream &os)
717{
718 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
719 SERIALIZE_SCALAR(clock);
720 SERIALIZE_SCALAR(pendingSmi);
721 SERIALIZE_SCALAR(smiVector);
722 SERIALIZE_SCALAR(pendingNmi);
723 SERIALIZE_SCALAR(nmiVector);
724 SERIALIZE_SCALAR(pendingExtInt);
725 SERIALIZE_SCALAR(extIntVector);
726 SERIALIZE_SCALAR(pendingInit);
727 SERIALIZE_SCALAR(initVector);
728 SERIALIZE_SCALAR(pendingStartup);
729 SERIALIZE_SCALAR(startupVector);
730 SERIALIZE_SCALAR(startedUp);
731 SERIALIZE_SCALAR(pendingUnmaskableInt);
732 SERIALIZE_SCALAR(pendingIPIs);
733 SERIALIZE_SCALAR(IRRV);
734 SERIALIZE_SCALAR(ISRV);
735 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
736 SERIALIZE_SCALAR(apicTimerEventScheduled);
737 Tick apicTimerEventTick = apicTimerEvent.when();
738 SERIALIZE_SCALAR(apicTimerEventTick);
739}
740
741void
742X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion)
743{
744 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
745 UNSERIALIZE_SCALAR(clock);
746 UNSERIALIZE_SCALAR(pendingSmi);
747 UNSERIALIZE_SCALAR(smiVector);
748 UNSERIALIZE_SCALAR(pendingNmi);
749 UNSERIALIZE_SCALAR(nmiVector);
750 UNSERIALIZE_SCALAR(pendingExtInt);
751 UNSERIALIZE_SCALAR(extIntVector);
752 UNSERIALIZE_SCALAR(pendingInit);
753 UNSERIALIZE_SCALAR(initVector);
754 UNSERIALIZE_SCALAR(pendingStartup);
755 UNSERIALIZE_SCALAR(startupVector);
756 UNSERIALIZE_SCALAR(startedUp);
757 UNSERIALIZE_SCALAR(pendingUnmaskableInt);
758 UNSERIALIZE_SCALAR(pendingIPIs);
759 UNSERIALIZE_SCALAR(IRRV);
760 UNSERIALIZE_SCALAR(ISRV);
761 bool apicTimerEventScheduled;
762 UNSERIALIZE_SCALAR(apicTimerEventScheduled);
763 if (apicTimerEventScheduled) {
764 Tick apicTimerEventTick;
765 UNSERIALIZE_SCALAR(apicTimerEventTick);
766 if (apicTimerEvent.scheduled()) {
767 reschedule(apicTimerEvent, apicTimerEventTick, true);
768 } else {
769 schedule(apicTimerEvent, apicTimerEventTick);
770 }
771 }
772}
773
774X86ISA::Interrupts *
775X86LocalApicParams::create()
776{
777 return new X86ISA::Interrupts(this);
778}
| 375}
376
377
378uint32_t
379X86ISA::Interrupts::readReg(ApicRegIndex reg)
380{
381 if (reg >= APIC_TRIGGER_MODE(0) &&
382 reg <= APIC_TRIGGER_MODE(15)) {
383 panic("Local APIC Trigger Mode registers are unimplemented.\n");
384 }
385 switch (reg) {
386 case APIC_ARBITRATION_PRIORITY:
387 panic("Local APIC Arbitration Priority register unimplemented.\n");
388 break;
389 case APIC_PROCESSOR_PRIORITY:
390 panic("Local APIC Processor Priority register unimplemented.\n");
391 break;
392 case APIC_ERROR_STATUS:
393 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
394 break;
395 case APIC_CURRENT_COUNT:
396 {
397 if (apicTimerEvent.scheduled()) {
398 assert(clock);
399 // Compute how many m5 ticks happen per count.
400 uint64_t ticksPerCount = clock *
401 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
402 // Compute how many m5 ticks are left.
403 uint64_t val = apicTimerEvent.when() - curTick();
404 // Turn that into a count.
405 val = (val + ticksPerCount - 1) / ticksPerCount;
406 return val;
407 } else {
408 return 0;
409 }
410 }
411 default:
412 break;
413 }
414 return regs[reg];
415}
416
417void
418X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
419{
420 uint32_t newVal = val;
421 if (reg >= APIC_IN_SERVICE(0) &&
422 reg <= APIC_IN_SERVICE(15)) {
423 panic("Local APIC In-Service registers are unimplemented.\n");
424 }
425 if (reg >= APIC_TRIGGER_MODE(0) &&
426 reg <= APIC_TRIGGER_MODE(15)) {
427 panic("Local APIC Trigger Mode registers are unimplemented.\n");
428 }
429 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
430 reg <= APIC_INTERRUPT_REQUEST(15)) {
431 panic("Local APIC Interrupt Request registers "
432 "are unimplemented.\n");
433 }
434 switch (reg) {
435 case APIC_ID:
436 newVal = val & 0xFF;
437 break;
438 case APIC_VERSION:
439 // The Local APIC Version register is read only.
440 return;
441 case APIC_TASK_PRIORITY:
442 newVal = val & 0xFF;
443 break;
444 case APIC_ARBITRATION_PRIORITY:
445 panic("Local APIC Arbitration Priority register unimplemented.\n");
446 break;
447 case APIC_PROCESSOR_PRIORITY:
448 panic("Local APIC Processor Priority register unimplemented.\n");
449 break;
450 case APIC_EOI:
451 // Remove the interrupt that just completed from the local apic state.
452 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
453 updateISRV();
454 return;
455 case APIC_LOGICAL_DESTINATION:
456 newVal = val & 0xFF000000;
457 break;
458 case APIC_DESTINATION_FORMAT:
459 newVal = val | 0x0FFFFFFF;
460 break;
461 case APIC_SPURIOUS_INTERRUPT_VECTOR:
462 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
463 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
464 if (val & (1 << 9))
465 warn("Focus processor checking not implemented.\n");
466 break;
467 case APIC_ERROR_STATUS:
468 {
469 if (regs[APIC_INTERNAL_STATE] & 0x1) {
470 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
471 newVal = 0;
472 } else {
473 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
474 return;
475 }
476
477 }
478 break;
479 case APIC_INTERRUPT_COMMAND_LOW:
480 {
481 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
482 // Check if we're already sending an IPI.
483 if (low.deliveryStatus) {
484 newVal = low;
485 break;
486 }
487 low = val;
488 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
489 // Record that an IPI is being sent.
490 low.deliveryStatus = 1;
491 TriggerIntMessage message = 0;
492 message.destination = high.destination;
493 message.vector = low.vector;
494 message.deliveryMode = low.deliveryMode;
495 message.destMode = low.destMode;
496 message.level = low.level;
497 message.trigger = low.trigger;
498 bool timing = sys->getMemoryMode() == Enums::timing;
499 // Be careful no updates of the delivery status bit get lost.
500 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
501 ApicList apics;
502 int numContexts = sys->numContexts();
503 switch (low.destShorthand) {
504 case 0:
505 if (message.deliveryMode == DeliveryMode::LowestPriority) {
506 panic("Lowest priority delivery mode "
507 "IPIs aren't implemented.\n");
508 }
509 if (message.destMode == 1) {
510 int dest = message.destination;
511 hack_once("Assuming logical destinations are 1 << id.\n");
512 for (int i = 0; i < numContexts; i++) {
513 if (dest & 0x1)
514 apics.push_back(i);
515 dest = dest >> 1;
516 }
517 } else {
518 if (message.destination == 0xFF) {
519 for (int i = 0; i < numContexts; i++) {
520 if (i == initialApicId) {
521 requestInterrupt(message.vector,
522 message.deliveryMode, message.trigger);
523 } else {
524 apics.push_back(i);
525 }
526 }
527 } else {
528 if (message.destination == initialApicId) {
529 requestInterrupt(message.vector,
530 message.deliveryMode, message.trigger);
531 } else {
532 apics.push_back(message.destination);
533 }
534 }
535 }
536 break;
537 case 1:
538 newVal = val;
539 requestInterrupt(message.vector,
540 message.deliveryMode, message.trigger);
541 break;
542 case 2:
543 requestInterrupt(message.vector,
544 message.deliveryMode, message.trigger);
545 // Fall through
546 case 3:
547 {
548 for (int i = 0; i < numContexts; i++) {
549 if (i != initialApicId) {
550 apics.push_back(i);
551 }
552 }
553 }
554 break;
555 }
556 pendingIPIs += apics.size();
557 intPort->sendMessage(apics, message, timing);
558 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
559 }
560 break;
561 case APIC_LVT_TIMER:
562 case APIC_LVT_THERMAL_SENSOR:
563 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
564 case APIC_LVT_LINT0:
565 case APIC_LVT_LINT1:
566 case APIC_LVT_ERROR:
567 {
568 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
569 newVal = (val & ~readOnlyMask) |
570 (regs[reg] & readOnlyMask);
571 }
572 break;
573 case APIC_INITIAL_COUNT:
574 {
575 assert(clock);
576 newVal = bits(val, 31, 0);
577 // Compute how many timer ticks we're being programmed for.
578 uint64_t newCount = newVal *
579 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
580 // Schedule on the edge of the next tick plus the new count.
581 Tick offset = curTick() % clock;
582 if (offset) {
583 reschedule(apicTimerEvent,
584 curTick() + (newCount + 1) * clock - offset, true);
585 } else {
586 reschedule(apicTimerEvent,
587 curTick() + newCount * clock, true);
588 }
589 }
590 break;
591 case APIC_CURRENT_COUNT:
592 //Local APIC Current Count register is read only.
593 return;
594 case APIC_DIVIDE_CONFIGURATION:
595 newVal = val & 0xB;
596 break;
597 default:
598 break;
599 }
600 regs[reg] = newVal;
601 return;
602}
603
604
605X86ISA::Interrupts::Interrupts(Params * p) :
606 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
607 clock(0),
608 apicTimerEvent(this),
609 pendingSmi(false), smiVector(0),
610 pendingNmi(false), nmiVector(0),
611 pendingExtInt(false), extIntVector(0),
612 pendingInit(false), initVector(0),
613 pendingStartup(false), startupVector(0),
614 startedUp(false), pendingUnmaskableInt(false),
615 pendingIPIs(0), cpu(NULL)
616{
617 pioSize = PageBytes;
618 memset(regs, 0, sizeof(regs));
619 //Set the local apic DFR to the flat model.
620 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
621 ISRV = 0;
622 IRRV = 0;
623}
624
625
626bool
627X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
628{
629 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
630 if (pendingUnmaskableInt) {
631 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
632 return true;
633 }
634 if (rflags.intf) {
635 if (pendingExtInt) {
636 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
637 return true;
638 }
639 if (IRRV > ISRV && bits(IRRV, 7, 4) >
640 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
641 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
642 return true;
643 }
644 }
645 return false;
646}
647
648Fault
649X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
650{
651 assert(checkInterrupts(tc));
652 // These are all probably fairly uncommon, so we'll make them easier to
653 // check for.
654 if (pendingUnmaskableInt) {
655 if (pendingSmi) {
656 DPRINTF(LocalApic, "Generated SMI fault object.\n");
657 return new SystemManagementInterrupt();
658 } else if (pendingNmi) {
659 DPRINTF(LocalApic, "Generated NMI fault object.\n");
660 return new NonMaskableInterrupt(nmiVector);
661 } else if (pendingInit) {
662 DPRINTF(LocalApic, "Generated INIT fault object.\n");
663 return new InitInterrupt(initVector);
664 } else if (pendingStartup) {
665 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
666 return new StartupInterrupt(startupVector);
667 } else {
668 panic("pendingUnmaskableInt set, but no unmaskable "
669 "ints were pending.\n");
670 return NoFault;
671 }
672 } else if (pendingExtInt) {
673 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
674 return new ExternalInterrupt(extIntVector);
675 } else {
676 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
677 // The only thing left are fixed and lowest priority interrupts.
678 return new ExternalInterrupt(IRRV);
679 }
680}
681
682void
683X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
684{
685 assert(checkInterrupts(tc));
686 if (pendingUnmaskableInt) {
687 if (pendingSmi) {
688 DPRINTF(LocalApic, "SMI sent to core.\n");
689 pendingSmi = false;
690 } else if (pendingNmi) {
691 DPRINTF(LocalApic, "NMI sent to core.\n");
692 pendingNmi = false;
693 } else if (pendingInit) {
694 DPRINTF(LocalApic, "Init sent to core.\n");
695 pendingInit = false;
696 startedUp = false;
697 } else if (pendingStartup) {
698 DPRINTF(LocalApic, "SIPI sent to core.\n");
699 pendingStartup = false;
700 startedUp = true;
701 }
702 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
703 pendingUnmaskableInt = false;
704 } else if (pendingExtInt) {
705 pendingExtInt = false;
706 } else {
707 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
708 // Mark the interrupt as "in service".
709 ISRV = IRRV;
710 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
711 // Clear it out of the IRR.
712 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
713 updateIRRV();
714 }
715}
716
717void
718X86ISA::Interrupts::serialize(std::ostream &os)
719{
720 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
721 SERIALIZE_SCALAR(clock);
722 SERIALIZE_SCALAR(pendingSmi);
723 SERIALIZE_SCALAR(smiVector);
724 SERIALIZE_SCALAR(pendingNmi);
725 SERIALIZE_SCALAR(nmiVector);
726 SERIALIZE_SCALAR(pendingExtInt);
727 SERIALIZE_SCALAR(extIntVector);
728 SERIALIZE_SCALAR(pendingInit);
729 SERIALIZE_SCALAR(initVector);
730 SERIALIZE_SCALAR(pendingStartup);
731 SERIALIZE_SCALAR(startupVector);
732 SERIALIZE_SCALAR(startedUp);
733 SERIALIZE_SCALAR(pendingUnmaskableInt);
734 SERIALIZE_SCALAR(pendingIPIs);
735 SERIALIZE_SCALAR(IRRV);
736 SERIALIZE_SCALAR(ISRV);
737 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
738 SERIALIZE_SCALAR(apicTimerEventScheduled);
739 Tick apicTimerEventTick = apicTimerEvent.when();
740 SERIALIZE_SCALAR(apicTimerEventTick);
741}
742
743void
744X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion)
745{
746 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
747 UNSERIALIZE_SCALAR(clock);
748 UNSERIALIZE_SCALAR(pendingSmi);
749 UNSERIALIZE_SCALAR(smiVector);
750 UNSERIALIZE_SCALAR(pendingNmi);
751 UNSERIALIZE_SCALAR(nmiVector);
752 UNSERIALIZE_SCALAR(pendingExtInt);
753 UNSERIALIZE_SCALAR(extIntVector);
754 UNSERIALIZE_SCALAR(pendingInit);
755 UNSERIALIZE_SCALAR(initVector);
756 UNSERIALIZE_SCALAR(pendingStartup);
757 UNSERIALIZE_SCALAR(startupVector);
758 UNSERIALIZE_SCALAR(startedUp);
759 UNSERIALIZE_SCALAR(pendingUnmaskableInt);
760 UNSERIALIZE_SCALAR(pendingIPIs);
761 UNSERIALIZE_SCALAR(IRRV);
762 UNSERIALIZE_SCALAR(ISRV);
763 bool apicTimerEventScheduled;
764 UNSERIALIZE_SCALAR(apicTimerEventScheduled);
765 if (apicTimerEventScheduled) {
766 Tick apicTimerEventTick;
767 UNSERIALIZE_SCALAR(apicTimerEventTick);
768 if (apicTimerEvent.scheduled()) {
769 reschedule(apicTimerEvent, apicTimerEventTick, true);
770 } else {
771 schedule(apicTimerEvent, apicTimerEventTick);
772 }
773 }
774}
775
776X86ISA::Interrupts *
777X86LocalApicParams::create()
778{
779 return new X86ISA::Interrupts(this);
780}
|