1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/interrupts.hh"
41#include "arch/x86/intmessage.hh"
42#include "arch/x86/regs/apic.hh"
43#include "cpu/base.hh"
44#include "dev/x86/i82094aa.hh"
45#include "dev/x86/pc.hh"
46#include "dev/x86/south_bridge.hh"
47#include "mem/packet_access.hh"
48#include "sim/system.hh"
49
50int
51divideFromConf(uint32_t conf)
52{
53 // This figures out what division we want from the division configuration
54 // register in the local APIC. The encoding is a little odd but it can
55 // be deciphered fairly easily.
56 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
57 shift = (shift + 1) % 8;
58 return 1 << shift;
59}
60
61namespace X86ISA
62{
63
64ApicRegIndex
65decodeAddr(Addr paddr)
66{
67 ApicRegIndex regNum;
68 paddr &= ~mask(3);
69 switch (paddr)
70 {
71 case 0x20:
72 regNum = APIC_ID;
73 break;
74 case 0x30:
75 regNum = APIC_VERSION;
76 break;
77 case 0x80:
78 regNum = APIC_TASK_PRIORITY;
79 break;
80 case 0x90:
81 regNum = APIC_ARBITRATION_PRIORITY;
82 break;
83 case 0xA0:
84 regNum = APIC_PROCESSOR_PRIORITY;
85 break;
86 case 0xB0:
87 regNum = APIC_EOI;
88 break;
89 case 0xD0:
90 regNum = APIC_LOGICAL_DESTINATION;
91 break;
92 case 0xE0:
93 regNum = APIC_DESTINATION_FORMAT;
94 break;
95 case 0xF0:
96 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
97 break;
98 case 0x100:
99 case 0x108:
100 case 0x110:
101 case 0x118:
102 case 0x120:
103 case 0x128:
104 case 0x130:
105 case 0x138:
106 case 0x140:
107 case 0x148:
108 case 0x150:
109 case 0x158:
110 case 0x160:
111 case 0x168:
112 case 0x170:
113 case 0x178:
114 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
115 break;
116 case 0x180:
117 case 0x188:
118 case 0x190:
119 case 0x198:
120 case 0x1A0:
121 case 0x1A8:
122 case 0x1B0:
123 case 0x1B8:
124 case 0x1C0:
125 case 0x1C8:
126 case 0x1D0:
127 case 0x1D8:
128 case 0x1E0:
129 case 0x1E8:
130 case 0x1F0:
131 case 0x1F8:
132 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
133 break;
134 case 0x200:
135 case 0x208:
136 case 0x210:
137 case 0x218:
138 case 0x220:
139 case 0x228:
140 case 0x230:
141 case 0x238:
142 case 0x240:
143 case 0x248:
144 case 0x250:
145 case 0x258:
146 case 0x260:
147 case 0x268:
148 case 0x270:
149 case 0x278:
150 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
151 break;
152 case 0x280:
153 regNum = APIC_ERROR_STATUS;
154 break;
155 case 0x300:
156 regNum = APIC_INTERRUPT_COMMAND_LOW;
157 break;
158 case 0x310:
159 regNum = APIC_INTERRUPT_COMMAND_HIGH;
160 break;
161 case 0x320:
162 regNum = APIC_LVT_TIMER;
163 break;
164 case 0x330:
165 regNum = APIC_LVT_THERMAL_SENSOR;
166 break;
167 case 0x340:
168 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
169 break;
170 case 0x350:
171 regNum = APIC_LVT_LINT0;
172 break;
173 case 0x360:
174 regNum = APIC_LVT_LINT1;
175 break;
176 case 0x370:
177 regNum = APIC_LVT_ERROR;
178 break;
179 case 0x380:
180 regNum = APIC_INITIAL_COUNT;
181 break;
182 case 0x390:
183 regNum = APIC_CURRENT_COUNT;
184 break;
185 case 0x3E0:
186 regNum = APIC_DIVIDE_CONFIGURATION;
187 break;
188 default:
189 // A reserved register field.
190 panic("Accessed reserved register field %#x.\n", paddr);
191 break;
192 }
193 return regNum;
194}
195}
196
197Tick
198X86ISA::Interrupts::read(PacketPtr pkt)
199{
200 Addr offset = pkt->getAddr() - pioAddr;
201 //Make sure we're at least only accessing one register.
202 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
203 panic("Accessed more than one register at a time in the APIC!\n");
204 ApicRegIndex reg = decodeAddr(offset);
205 uint32_t val = htog(readReg(reg));
206 DPRINTF(LocalApic,
207 "Reading Local APIC register %d at offset %#x as %#x.\n",
208 reg, offset, val);
209 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
210 pkt->makeAtomicResponse();
211 return latency;
212}
213
214Tick
215X86ISA::Interrupts::write(PacketPtr pkt)
216{
217 Addr offset = pkt->getAddr() - pioAddr;
218 //Make sure we're at least only accessing one register.
219 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
220 panic("Accessed more than one register at a time in the APIC!\n");
221 ApicRegIndex reg = decodeAddr(offset);
222 uint32_t val = regs[reg];
223 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
224 DPRINTF(LocalApic,
225 "Writing Local APIC register %d at offset %#x as %#x.\n",
226 reg, offset, gtoh(val));
227 setReg(reg, gtoh(val));
228 pkt->makeAtomicResponse();
229 return latency;
230}
231void
232X86ISA::Interrupts::requestInterrupt(uint8_t vector,
233 uint8_t deliveryMode, bool level)
234{
235 /*
236 * Fixed and lowest-priority delivery mode interrupts are handled
237 * using the IRR/ISR registers, checking against the TPR, etc.
238 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
239 */
240 if (deliveryMode == DeliveryMode::Fixed ||
241 deliveryMode == DeliveryMode::LowestPriority) {
242 DPRINTF(LocalApic, "Interrupt is an %s.\n",
243 DeliveryMode::names[deliveryMode]);
244 // Queue up the interrupt in the IRR.
245 if (vector > IRRV)
246 IRRV = vector;
247 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
248 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
249 if (level) {
250 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
251 } else {
252 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253 }
254 }
255 } else if (!DeliveryMode::isReserved(deliveryMode)) {
256 DPRINTF(LocalApic, "Interrupt is an %s.\n",
257 DeliveryMode::names[deliveryMode]);
258 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
259 pendingUnmaskableInt = pendingSmi = true;
260 smiVector = vector;
261 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
262 pendingUnmaskableInt = pendingNmi = true;
263 nmiVector = vector;
264 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
265 pendingExtInt = true;
266 extIntVector = vector;
267 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
268 pendingUnmaskableInt = pendingInit = true;
269 initVector = vector;
270 } else if (deliveryMode == DeliveryMode::SIPI &&
271 !pendingStartup && !startedUp) {
272 pendingUnmaskableInt = pendingStartup = true;
273 startupVector = vector;
274 }
275 }
276 cpu->wakeup();
277}
278
279
280void
281X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
282{
283 assert(newCPU);
284 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
285 panic("Local APICs can't be moved between CPUs"
286 " with different IDs.\n");
287 }
288 cpu = newCPU;
289 initialApicId = cpu->cpuId();
290 regs[APIC_ID] = (initialApicId << 24);
291}
292
293
294void
295X86ISA::Interrupts::init()
296{
297 BasicPioDevice::init();
298 Pc * pc = dynamic_cast<Pc *>(platform);
299 assert(pc);
300 pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
301}
302
303
304Tick
305X86ISA::Interrupts::recvMessage(PacketPtr pkt)
306{
307 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
308 assert(pkt->cmd == MemCmd::MessageReq);
309 switch(offset)
310 {
311 case 0:
312 {
313 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
314 DPRINTF(LocalApic,
315 "Got Trigger Interrupt message with vector %#x.\n",
316 message.vector);
317
318 requestInterrupt(message.vector,
319 message.deliveryMode, message.trigger);
320 }
321 break;
322 default:
323 panic("Local apic got unknown interrupt message at offset %#x.\n",
324 offset);
325 break;
326 }
327 pkt->makeAtomicResponse();
328 return latency;
329}
330
331
332Tick
333X86ISA::Interrupts::recvResponse(PacketPtr pkt)
334{
335 assert(!pkt->isError());
336 assert(pkt->cmd == MemCmd::MessageResp);
337 if (--pendingIPIs == 0) {
338 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
339 // Record that the ICR is now idle.
340 low.deliveryStatus = 0;
341 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
342 }
343 DPRINTF(LocalApic, "ICR is now idle.\n");
344 return 0;
345}
346
347
348void
349X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
350{
351 range_list.clear();
352 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
353 x86LocalAPICAddress(initialApicId, 0) +
354 PageBytes);
355 range_list.push_back(range);
356 pioAddr = range.start;
357}
358
359
360void
361X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
362{
363 range_list.clear();
364 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
365 x86InterruptAddress(initialApicId, 0) +
366 PhysAddrAPICRangeSize));
367}
368
369
370uint32_t
371X86ISA::Interrupts::readReg(ApicRegIndex reg)
372{
373 if (reg >= APIC_TRIGGER_MODE(0) &&
374 reg <= APIC_TRIGGER_MODE(15)) {
375 panic("Local APIC Trigger Mode registers are unimplemented.\n");
376 }
377 switch (reg) {
378 case APIC_ARBITRATION_PRIORITY:
379 panic("Local APIC Arbitration Priority register unimplemented.\n");
380 break;
381 case APIC_PROCESSOR_PRIORITY:
382 panic("Local APIC Processor Priority register unimplemented.\n");
383 break;
384 case APIC_ERROR_STATUS:
385 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
386 break;
387 case APIC_CURRENT_COUNT:
388 {
389 if (apicTimerEvent.scheduled()) {
390 assert(clock);
391 // Compute how many m5 ticks happen per count.
392 uint64_t ticksPerCount = clock *
393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
394 // Compute how many m5 ticks are left.
395 uint64_t val = apicTimerEvent.when() - curTick();
396 // Turn that into a count.
397 val = (val + ticksPerCount - 1) / ticksPerCount;
398 return val;
399 } else {
400 return 0;
401 }
402 }
403 default:
404 break;
405 }
406 return regs[reg];
407}
408
409void
410X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
411{
412 uint32_t newVal = val;
413 if (reg >= APIC_IN_SERVICE(0) &&
414 reg <= APIC_IN_SERVICE(15)) {
415 panic("Local APIC In-Service registers are unimplemented.\n");
416 }
417 if (reg >= APIC_TRIGGER_MODE(0) &&
418 reg <= APIC_TRIGGER_MODE(15)) {
419 panic("Local APIC Trigger Mode registers are unimplemented.\n");
420 }
421 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
422 reg <= APIC_INTERRUPT_REQUEST(15)) {
423 panic("Local APIC Interrupt Request registers "
424 "are unimplemented.\n");
425 }
426 switch (reg) {
427 case APIC_ID:
428 newVal = val & 0xFF;
429 break;
430 case APIC_VERSION:
431 // The Local APIC Version register is read only.
432 return;
433 case APIC_TASK_PRIORITY:
434 newVal = val & 0xFF;
435 break;
436 case APIC_ARBITRATION_PRIORITY:
437 panic("Local APIC Arbitration Priority register unimplemented.\n");
438 break;
439 case APIC_PROCESSOR_PRIORITY:
440 panic("Local APIC Processor Priority register unimplemented.\n");
441 break;
442 case APIC_EOI:
443 // Remove the interrupt that just completed from the local apic state.
444 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
445 updateISRV();
446 return;
447 case APIC_LOGICAL_DESTINATION:
448 newVal = val & 0xFF000000;
449 break;
450 case APIC_DESTINATION_FORMAT:
451 newVal = val | 0x0FFFFFFF;
452 break;
453 case APIC_SPURIOUS_INTERRUPT_VECTOR:
454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
455 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
456 if (val & (1 << 9))
457 warn("Focus processor checking not implemented.\n");
458 break;
459 case APIC_ERROR_STATUS:
460 {
461 if (regs[APIC_INTERNAL_STATE] & 0x1) {
462 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
463 newVal = 0;
464 } else {
465 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
466 return;
467 }
468
469 }
470 break;
471 case APIC_INTERRUPT_COMMAND_LOW:
472 {
473 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
474 // Check if we're already sending an IPI.
475 if (low.deliveryStatus) {
476 newVal = low;
477 break;
478 }
479 low = val;
480 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
481 // Record that an IPI is being sent.
482 low.deliveryStatus = 1;
483 TriggerIntMessage message = 0;
484 message.destination = high.destination;
485 message.vector = low.vector;
486 message.deliveryMode = low.deliveryMode;
487 message.destMode = low.destMode;
488 message.level = low.level;
489 message.trigger = low.trigger;
490 bool timing = sys->getMemoryMode() == Enums::timing;
491 // Be careful no updates of the delivery status bit get lost.
492 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
493 ApicList apics;
494 int numContexts = sys->numContexts();
495 switch (low.destShorthand) {
496 case 0:
497 if (message.deliveryMode == DeliveryMode::LowestPriority) {
498 panic("Lowest priority delivery mode "
499 "IPIs aren't implemented.\n");
500 }
501 if (message.destMode == 1) {
502 int dest = message.destination;
503 hack_once("Assuming logical destinations are 1 << id.\n");
504 for (int i = 0; i < numContexts; i++) {
505 if (dest & 0x1)
506 apics.push_back(i);
507 dest = dest >> 1;
508 }
509 } else {
510 if (message.destination == 0xFF) {
511 for (int i = 0; i < numContexts; i++) {
512 if (i == initialApicId) {
513 requestInterrupt(message.vector,
514 message.deliveryMode, message.trigger);
515 } else {
516 apics.push_back(i);
517 }
518 }
519 } else {
520 if (message.destination == initialApicId) {
521 requestInterrupt(message.vector,
522 message.deliveryMode, message.trigger);
523 } else {
524 apics.push_back(message.destination);
525 }
526 }
527 }
528 break;
529 case 1:
530 newVal = val;
531 requestInterrupt(message.vector,
532 message.deliveryMode, message.trigger);
533 break;
534 case 2:
535 requestInterrupt(message.vector,
536 message.deliveryMode, message.trigger);
537 // Fall through
538 case 3:
539 {
540 for (int i = 0; i < numContexts; i++) {
541 if (i != initialApicId) {
542 apics.push_back(i);
543 }
544 }
545 }
546 break;
547 }
548 pendingIPIs += apics.size();
549 intPort->sendMessage(apics, message, timing);
550 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
551 }
552 break;
553 case APIC_LVT_TIMER:
554 case APIC_LVT_THERMAL_SENSOR:
555 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
556 case APIC_LVT_LINT0:
557 case APIC_LVT_LINT1:
558 case APIC_LVT_ERROR:
559 {
560 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
561 newVal = (val & ~readOnlyMask) |
562 (regs[reg] & readOnlyMask);
563 }
564 break;
565 case APIC_INITIAL_COUNT:
566 {
567 assert(clock);
568 newVal = bits(val, 31, 0);
569 // Compute how many timer ticks we're being programmed for.
570 uint64_t newCount = newVal *
571 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
572 // Schedule on the edge of the next tick plus the new count.
573 Tick offset = curTick() % clock;
574 if (offset) {
575 reschedule(apicTimerEvent,
576 curTick() + (newCount + 1) * clock - offset, true);
577 } else {
578 reschedule(apicTimerEvent,
579 curTick() + newCount * clock, true);
580 }
581 }
582 break;
583 case APIC_CURRENT_COUNT:
584 //Local APIC Current Count register is read only.
585 return;
586 case APIC_DIVIDE_CONFIGURATION:
587 newVal = val & 0xB;
588 break;
589 default:
590 break;
591 }
592 regs[reg] = newVal;
593 return;
594}
595
596
597X86ISA::Interrupts::Interrupts(Params * p) :
598 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
599 clock(0),
600 apicTimerEvent(this),
601 pendingSmi(false), smiVector(0),
602 pendingNmi(false), nmiVector(0),
603 pendingExtInt(false), extIntVector(0),
604 pendingInit(false), initVector(0),
605 pendingStartup(false), startupVector(0),
606 startedUp(false), pendingUnmaskableInt(false),
607 pendingIPIs(0), cpu(NULL)
608{
609 pioSize = PageBytes;
610 memset(regs, 0, sizeof(regs));
611 //Set the local apic DFR to the flat model.
612 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
613 ISRV = 0;
614 IRRV = 0;
615}
616
617
618bool
619X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
620{
621 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
622 if (pendingUnmaskableInt) {
623 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
624 return true;
625 }
626 if (rflags.intf) {
627 if (pendingExtInt) {
628 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
629 return true;
630 }
631 if (IRRV > ISRV && bits(IRRV, 7, 4) >
632 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
633 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
634 return true;
635 }
636 }
637 return false;
638}
639
640Fault
641X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
642{
643 assert(checkInterrupts(tc));
644 // These are all probably fairly uncommon, so we'll make them easier to
645 // check for.
646 if (pendingUnmaskableInt) {
647 if (pendingSmi) {
648 DPRINTF(LocalApic, "Generated SMI fault object.\n");
649 return new SystemManagementInterrupt();
650 } else if (pendingNmi) {
651 DPRINTF(LocalApic, "Generated NMI fault object.\n");
652 return new NonMaskableInterrupt(nmiVector);
653 } else if (pendingInit) {
654 DPRINTF(LocalApic, "Generated INIT fault object.\n");
655 return new InitInterrupt(initVector);
656 } else if (pendingStartup) {
657 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
658 return new StartupInterrupt(startupVector);
659 } else {
660 panic("pendingUnmaskableInt set, but no unmaskable "
661 "ints were pending.\n");
662 return NoFault;
663 }
664 } else if (pendingExtInt) {
665 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
666 return new ExternalInterrupt(extIntVector);
667 } else {
668 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
669 // The only thing left are fixed and lowest priority interrupts.
670 return new ExternalInterrupt(IRRV);
671 }
672}
673
674void
675X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
676{
677 assert(checkInterrupts(tc));
678 if (pendingUnmaskableInt) {
679 if (pendingSmi) {
680 DPRINTF(LocalApic, "SMI sent to core.\n");
681 pendingSmi = false;
682 } else if (pendingNmi) {
683 DPRINTF(LocalApic, "NMI sent to core.\n");
684 pendingNmi = false;
685 } else if (pendingInit) {
686 DPRINTF(LocalApic, "Init sent to core.\n");
687 pendingInit = false;
688 startedUp = false;
689 } else if (pendingStartup) {
690 DPRINTF(LocalApic, "SIPI sent to core.\n");
691 pendingStartup = false;
692 startedUp = true;
693 }
694 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
695 pendingUnmaskableInt = false;
696 } else if (pendingExtInt) {
697 pendingExtInt = false;
698 } else {
699 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
700 // Mark the interrupt as "in service".
701 ISRV = IRRV;
702 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
703 // Clear it out of the IRR.
704 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
705 updateIRRV();
706 }
707}
708
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/interrupts.hh"
41#include "arch/x86/intmessage.hh"
42#include "arch/x86/regs/apic.hh"
43#include "cpu/base.hh"
44#include "dev/x86/i82094aa.hh"
45#include "dev/x86/pc.hh"
46#include "dev/x86/south_bridge.hh"
47#include "mem/packet_access.hh"
48#include "sim/system.hh"
49
50int
51divideFromConf(uint32_t conf)
52{
53 // This figures out what division we want from the division configuration
54 // register in the local APIC. The encoding is a little odd but it can
55 // be deciphered fairly easily.
56 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
57 shift = (shift + 1) % 8;
58 return 1 << shift;
59}
60
61namespace X86ISA
62{
63
64ApicRegIndex
65decodeAddr(Addr paddr)
66{
67 ApicRegIndex regNum;
68 paddr &= ~mask(3);
69 switch (paddr)
70 {
71 case 0x20:
72 regNum = APIC_ID;
73 break;
74 case 0x30:
75 regNum = APIC_VERSION;
76 break;
77 case 0x80:
78 regNum = APIC_TASK_PRIORITY;
79 break;
80 case 0x90:
81 regNum = APIC_ARBITRATION_PRIORITY;
82 break;
83 case 0xA0:
84 regNum = APIC_PROCESSOR_PRIORITY;
85 break;
86 case 0xB0:
87 regNum = APIC_EOI;
88 break;
89 case 0xD0:
90 regNum = APIC_LOGICAL_DESTINATION;
91 break;
92 case 0xE0:
93 regNum = APIC_DESTINATION_FORMAT;
94 break;
95 case 0xF0:
96 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
97 break;
98 case 0x100:
99 case 0x108:
100 case 0x110:
101 case 0x118:
102 case 0x120:
103 case 0x128:
104 case 0x130:
105 case 0x138:
106 case 0x140:
107 case 0x148:
108 case 0x150:
109 case 0x158:
110 case 0x160:
111 case 0x168:
112 case 0x170:
113 case 0x178:
114 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
115 break;
116 case 0x180:
117 case 0x188:
118 case 0x190:
119 case 0x198:
120 case 0x1A0:
121 case 0x1A8:
122 case 0x1B0:
123 case 0x1B8:
124 case 0x1C0:
125 case 0x1C8:
126 case 0x1D0:
127 case 0x1D8:
128 case 0x1E0:
129 case 0x1E8:
130 case 0x1F0:
131 case 0x1F8:
132 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
133 break;
134 case 0x200:
135 case 0x208:
136 case 0x210:
137 case 0x218:
138 case 0x220:
139 case 0x228:
140 case 0x230:
141 case 0x238:
142 case 0x240:
143 case 0x248:
144 case 0x250:
145 case 0x258:
146 case 0x260:
147 case 0x268:
148 case 0x270:
149 case 0x278:
150 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
151 break;
152 case 0x280:
153 regNum = APIC_ERROR_STATUS;
154 break;
155 case 0x300:
156 regNum = APIC_INTERRUPT_COMMAND_LOW;
157 break;
158 case 0x310:
159 regNum = APIC_INTERRUPT_COMMAND_HIGH;
160 break;
161 case 0x320:
162 regNum = APIC_LVT_TIMER;
163 break;
164 case 0x330:
165 regNum = APIC_LVT_THERMAL_SENSOR;
166 break;
167 case 0x340:
168 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
169 break;
170 case 0x350:
171 regNum = APIC_LVT_LINT0;
172 break;
173 case 0x360:
174 regNum = APIC_LVT_LINT1;
175 break;
176 case 0x370:
177 regNum = APIC_LVT_ERROR;
178 break;
179 case 0x380:
180 regNum = APIC_INITIAL_COUNT;
181 break;
182 case 0x390:
183 regNum = APIC_CURRENT_COUNT;
184 break;
185 case 0x3E0:
186 regNum = APIC_DIVIDE_CONFIGURATION;
187 break;
188 default:
189 // A reserved register field.
190 panic("Accessed reserved register field %#x.\n", paddr);
191 break;
192 }
193 return regNum;
194}
195}
196
197Tick
198X86ISA::Interrupts::read(PacketPtr pkt)
199{
200 Addr offset = pkt->getAddr() - pioAddr;
201 //Make sure we're at least only accessing one register.
202 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
203 panic("Accessed more than one register at a time in the APIC!\n");
204 ApicRegIndex reg = decodeAddr(offset);
205 uint32_t val = htog(readReg(reg));
206 DPRINTF(LocalApic,
207 "Reading Local APIC register %d at offset %#x as %#x.\n",
208 reg, offset, val);
209 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
210 pkt->makeAtomicResponse();
211 return latency;
212}
213
214Tick
215X86ISA::Interrupts::write(PacketPtr pkt)
216{
217 Addr offset = pkt->getAddr() - pioAddr;
218 //Make sure we're at least only accessing one register.
219 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
220 panic("Accessed more than one register at a time in the APIC!\n");
221 ApicRegIndex reg = decodeAddr(offset);
222 uint32_t val = regs[reg];
223 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
224 DPRINTF(LocalApic,
225 "Writing Local APIC register %d at offset %#x as %#x.\n",
226 reg, offset, gtoh(val));
227 setReg(reg, gtoh(val));
228 pkt->makeAtomicResponse();
229 return latency;
230}
231void
232X86ISA::Interrupts::requestInterrupt(uint8_t vector,
233 uint8_t deliveryMode, bool level)
234{
235 /*
236 * Fixed and lowest-priority delivery mode interrupts are handled
237 * using the IRR/ISR registers, checking against the TPR, etc.
238 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
239 */
240 if (deliveryMode == DeliveryMode::Fixed ||
241 deliveryMode == DeliveryMode::LowestPriority) {
242 DPRINTF(LocalApic, "Interrupt is an %s.\n",
243 DeliveryMode::names[deliveryMode]);
244 // Queue up the interrupt in the IRR.
245 if (vector > IRRV)
246 IRRV = vector;
247 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
248 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
249 if (level) {
250 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
251 } else {
252 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253 }
254 }
255 } else if (!DeliveryMode::isReserved(deliveryMode)) {
256 DPRINTF(LocalApic, "Interrupt is an %s.\n",
257 DeliveryMode::names[deliveryMode]);
258 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
259 pendingUnmaskableInt = pendingSmi = true;
260 smiVector = vector;
261 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
262 pendingUnmaskableInt = pendingNmi = true;
263 nmiVector = vector;
264 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
265 pendingExtInt = true;
266 extIntVector = vector;
267 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
268 pendingUnmaskableInt = pendingInit = true;
269 initVector = vector;
270 } else if (deliveryMode == DeliveryMode::SIPI &&
271 !pendingStartup && !startedUp) {
272 pendingUnmaskableInt = pendingStartup = true;
273 startupVector = vector;
274 }
275 }
276 cpu->wakeup();
277}
278
279
280void
281X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
282{
283 assert(newCPU);
284 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
285 panic("Local APICs can't be moved between CPUs"
286 " with different IDs.\n");
287 }
288 cpu = newCPU;
289 initialApicId = cpu->cpuId();
290 regs[APIC_ID] = (initialApicId << 24);
291}
292
293
294void
295X86ISA::Interrupts::init()
296{
297 BasicPioDevice::init();
298 Pc * pc = dynamic_cast<Pc *>(platform);
299 assert(pc);
300 pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
301}
302
303
304Tick
305X86ISA::Interrupts::recvMessage(PacketPtr pkt)
306{
307 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
308 assert(pkt->cmd == MemCmd::MessageReq);
309 switch(offset)
310 {
311 case 0:
312 {
313 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
314 DPRINTF(LocalApic,
315 "Got Trigger Interrupt message with vector %#x.\n",
316 message.vector);
317
318 requestInterrupt(message.vector,
319 message.deliveryMode, message.trigger);
320 }
321 break;
322 default:
323 panic("Local apic got unknown interrupt message at offset %#x.\n",
324 offset);
325 break;
326 }
327 pkt->makeAtomicResponse();
328 return latency;
329}
330
331
332Tick
333X86ISA::Interrupts::recvResponse(PacketPtr pkt)
334{
335 assert(!pkt->isError());
336 assert(pkt->cmd == MemCmd::MessageResp);
337 if (--pendingIPIs == 0) {
338 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
339 // Record that the ICR is now idle.
340 low.deliveryStatus = 0;
341 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
342 }
343 DPRINTF(LocalApic, "ICR is now idle.\n");
344 return 0;
345}
346
347
348void
349X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
350{
351 range_list.clear();
352 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
353 x86LocalAPICAddress(initialApicId, 0) +
354 PageBytes);
355 range_list.push_back(range);
356 pioAddr = range.start;
357}
358
359
360void
361X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
362{
363 range_list.clear();
364 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
365 x86InterruptAddress(initialApicId, 0) +
366 PhysAddrAPICRangeSize));
367}
368
369
370uint32_t
371X86ISA::Interrupts::readReg(ApicRegIndex reg)
372{
373 if (reg >= APIC_TRIGGER_MODE(0) &&
374 reg <= APIC_TRIGGER_MODE(15)) {
375 panic("Local APIC Trigger Mode registers are unimplemented.\n");
376 }
377 switch (reg) {
378 case APIC_ARBITRATION_PRIORITY:
379 panic("Local APIC Arbitration Priority register unimplemented.\n");
380 break;
381 case APIC_PROCESSOR_PRIORITY:
382 panic("Local APIC Processor Priority register unimplemented.\n");
383 break;
384 case APIC_ERROR_STATUS:
385 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
386 break;
387 case APIC_CURRENT_COUNT:
388 {
389 if (apicTimerEvent.scheduled()) {
390 assert(clock);
391 // Compute how many m5 ticks happen per count.
392 uint64_t ticksPerCount = clock *
393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
394 // Compute how many m5 ticks are left.
395 uint64_t val = apicTimerEvent.when() - curTick();
396 // Turn that into a count.
397 val = (val + ticksPerCount - 1) / ticksPerCount;
398 return val;
399 } else {
400 return 0;
401 }
402 }
403 default:
404 break;
405 }
406 return regs[reg];
407}
408
409void
410X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
411{
412 uint32_t newVal = val;
413 if (reg >= APIC_IN_SERVICE(0) &&
414 reg <= APIC_IN_SERVICE(15)) {
415 panic("Local APIC In-Service registers are unimplemented.\n");
416 }
417 if (reg >= APIC_TRIGGER_MODE(0) &&
418 reg <= APIC_TRIGGER_MODE(15)) {
419 panic("Local APIC Trigger Mode registers are unimplemented.\n");
420 }
421 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
422 reg <= APIC_INTERRUPT_REQUEST(15)) {
423 panic("Local APIC Interrupt Request registers "
424 "are unimplemented.\n");
425 }
426 switch (reg) {
427 case APIC_ID:
428 newVal = val & 0xFF;
429 break;
430 case APIC_VERSION:
431 // The Local APIC Version register is read only.
432 return;
433 case APIC_TASK_PRIORITY:
434 newVal = val & 0xFF;
435 break;
436 case APIC_ARBITRATION_PRIORITY:
437 panic("Local APIC Arbitration Priority register unimplemented.\n");
438 break;
439 case APIC_PROCESSOR_PRIORITY:
440 panic("Local APIC Processor Priority register unimplemented.\n");
441 break;
442 case APIC_EOI:
443 // Remove the interrupt that just completed from the local apic state.
444 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
445 updateISRV();
446 return;
447 case APIC_LOGICAL_DESTINATION:
448 newVal = val & 0xFF000000;
449 break;
450 case APIC_DESTINATION_FORMAT:
451 newVal = val | 0x0FFFFFFF;
452 break;
453 case APIC_SPURIOUS_INTERRUPT_VECTOR:
454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
455 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
456 if (val & (1 << 9))
457 warn("Focus processor checking not implemented.\n");
458 break;
459 case APIC_ERROR_STATUS:
460 {
461 if (regs[APIC_INTERNAL_STATE] & 0x1) {
462 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
463 newVal = 0;
464 } else {
465 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
466 return;
467 }
468
469 }
470 break;
471 case APIC_INTERRUPT_COMMAND_LOW:
472 {
473 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
474 // Check if we're already sending an IPI.
475 if (low.deliveryStatus) {
476 newVal = low;
477 break;
478 }
479 low = val;
480 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
481 // Record that an IPI is being sent.
482 low.deliveryStatus = 1;
483 TriggerIntMessage message = 0;
484 message.destination = high.destination;
485 message.vector = low.vector;
486 message.deliveryMode = low.deliveryMode;
487 message.destMode = low.destMode;
488 message.level = low.level;
489 message.trigger = low.trigger;
490 bool timing = sys->getMemoryMode() == Enums::timing;
491 // Be careful no updates of the delivery status bit get lost.
492 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
493 ApicList apics;
494 int numContexts = sys->numContexts();
495 switch (low.destShorthand) {
496 case 0:
497 if (message.deliveryMode == DeliveryMode::LowestPriority) {
498 panic("Lowest priority delivery mode "
499 "IPIs aren't implemented.\n");
500 }
501 if (message.destMode == 1) {
502 int dest = message.destination;
503 hack_once("Assuming logical destinations are 1 << id.\n");
504 for (int i = 0; i < numContexts; i++) {
505 if (dest & 0x1)
506 apics.push_back(i);
507 dest = dest >> 1;
508 }
509 } else {
510 if (message.destination == 0xFF) {
511 for (int i = 0; i < numContexts; i++) {
512 if (i == initialApicId) {
513 requestInterrupt(message.vector,
514 message.deliveryMode, message.trigger);
515 } else {
516 apics.push_back(i);
517 }
518 }
519 } else {
520 if (message.destination == initialApicId) {
521 requestInterrupt(message.vector,
522 message.deliveryMode, message.trigger);
523 } else {
524 apics.push_back(message.destination);
525 }
526 }
527 }
528 break;
529 case 1:
530 newVal = val;
531 requestInterrupt(message.vector,
532 message.deliveryMode, message.trigger);
533 break;
534 case 2:
535 requestInterrupt(message.vector,
536 message.deliveryMode, message.trigger);
537 // Fall through
538 case 3:
539 {
540 for (int i = 0; i < numContexts; i++) {
541 if (i != initialApicId) {
542 apics.push_back(i);
543 }
544 }
545 }
546 break;
547 }
548 pendingIPIs += apics.size();
549 intPort->sendMessage(apics, message, timing);
550 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
551 }
552 break;
553 case APIC_LVT_TIMER:
554 case APIC_LVT_THERMAL_SENSOR:
555 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
556 case APIC_LVT_LINT0:
557 case APIC_LVT_LINT1:
558 case APIC_LVT_ERROR:
559 {
560 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
561 newVal = (val & ~readOnlyMask) |
562 (regs[reg] & readOnlyMask);
563 }
564 break;
565 case APIC_INITIAL_COUNT:
566 {
567 assert(clock);
568 newVal = bits(val, 31, 0);
569 // Compute how many timer ticks we're being programmed for.
570 uint64_t newCount = newVal *
571 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
572 // Schedule on the edge of the next tick plus the new count.
573 Tick offset = curTick() % clock;
574 if (offset) {
575 reschedule(apicTimerEvent,
576 curTick() + (newCount + 1) * clock - offset, true);
577 } else {
578 reschedule(apicTimerEvent,
579 curTick() + newCount * clock, true);
580 }
581 }
582 break;
583 case APIC_CURRENT_COUNT:
584 //Local APIC Current Count register is read only.
585 return;
586 case APIC_DIVIDE_CONFIGURATION:
587 newVal = val & 0xB;
588 break;
589 default:
590 break;
591 }
592 regs[reg] = newVal;
593 return;
594}
595
596
597X86ISA::Interrupts::Interrupts(Params * p) :
598 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
599 clock(0),
600 apicTimerEvent(this),
601 pendingSmi(false), smiVector(0),
602 pendingNmi(false), nmiVector(0),
603 pendingExtInt(false), extIntVector(0),
604 pendingInit(false), initVector(0),
605 pendingStartup(false), startupVector(0),
606 startedUp(false), pendingUnmaskableInt(false),
607 pendingIPIs(0), cpu(NULL)
608{
609 pioSize = PageBytes;
610 memset(regs, 0, sizeof(regs));
611 //Set the local apic DFR to the flat model.
612 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
613 ISRV = 0;
614 IRRV = 0;
615}
616
617
618bool
619X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
620{
621 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
622 if (pendingUnmaskableInt) {
623 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
624 return true;
625 }
626 if (rflags.intf) {
627 if (pendingExtInt) {
628 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
629 return true;
630 }
631 if (IRRV > ISRV && bits(IRRV, 7, 4) >
632 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
633 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
634 return true;
635 }
636 }
637 return false;
638}
639
640Fault
641X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
642{
643 assert(checkInterrupts(tc));
644 // These are all probably fairly uncommon, so we'll make them easier to
645 // check for.
646 if (pendingUnmaskableInt) {
647 if (pendingSmi) {
648 DPRINTF(LocalApic, "Generated SMI fault object.\n");
649 return new SystemManagementInterrupt();
650 } else if (pendingNmi) {
651 DPRINTF(LocalApic, "Generated NMI fault object.\n");
652 return new NonMaskableInterrupt(nmiVector);
653 } else if (pendingInit) {
654 DPRINTF(LocalApic, "Generated INIT fault object.\n");
655 return new InitInterrupt(initVector);
656 } else if (pendingStartup) {
657 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
658 return new StartupInterrupt(startupVector);
659 } else {
660 panic("pendingUnmaskableInt set, but no unmaskable "
661 "ints were pending.\n");
662 return NoFault;
663 }
664 } else if (pendingExtInt) {
665 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
666 return new ExternalInterrupt(extIntVector);
667 } else {
668 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
669 // The only thing left are fixed and lowest priority interrupts.
670 return new ExternalInterrupt(IRRV);
671 }
672}
673
674void
675X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
676{
677 assert(checkInterrupts(tc));
678 if (pendingUnmaskableInt) {
679 if (pendingSmi) {
680 DPRINTF(LocalApic, "SMI sent to core.\n");
681 pendingSmi = false;
682 } else if (pendingNmi) {
683 DPRINTF(LocalApic, "NMI sent to core.\n");
684 pendingNmi = false;
685 } else if (pendingInit) {
686 DPRINTF(LocalApic, "Init sent to core.\n");
687 pendingInit = false;
688 startedUp = false;
689 } else if (pendingStartup) {
690 DPRINTF(LocalApic, "SIPI sent to core.\n");
691 pendingStartup = false;
692 startedUp = true;
693 }
694 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
695 pendingUnmaskableInt = false;
696 } else if (pendingExtInt) {
697 pendingExtInt = false;
698 } else {
699 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
700 // Mark the interrupt as "in service".
701 ISRV = IRRV;
702 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
703 // Clear it out of the IRR.
704 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
705 updateIRRV();
706 }
707}
708
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