1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "dev/x86/i82094aa.hh"
63#include "dev/x86/pc.hh"
64#include "dev/x86/south_bridge.hh"
65#include "mem/packet_access.hh"
66#include "sim/system.hh"
67
68int
69divideFromConf(uint32_t conf)
70{
71 // This figures out what division we want from the division configuration
72 // register in the local APIC. The encoding is a little odd but it can
73 // be deciphered fairly easily.
74 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
75 shift = (shift + 1) % 8;
76 return 1 << shift;
77}
78
79namespace X86ISA
80{
81
82ApicRegIndex
83decodeAddr(Addr paddr)
84{
85 ApicRegIndex regNum;
86 paddr &= ~mask(3);
87 switch (paddr)
88 {
89 case 0x20:
90 regNum = APIC_ID;
91 break;
92 case 0x30:
93 regNum = APIC_VERSION;
94 break;
95 case 0x80:
96 regNum = APIC_TASK_PRIORITY;
97 break;
98 case 0x90:
99 regNum = APIC_ARBITRATION_PRIORITY;
100 break;
101 case 0xA0:
102 regNum = APIC_PROCESSOR_PRIORITY;
103 break;
104 case 0xB0:
105 regNum = APIC_EOI;
106 break;
107 case 0xD0:
108 regNum = APIC_LOGICAL_DESTINATION;
109 break;
110 case 0xE0:
111 regNum = APIC_DESTINATION_FORMAT;
112 break;
113 case 0xF0:
114 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
115 break;
116 case 0x100:
117 case 0x108:
118 case 0x110:
119 case 0x118:
120 case 0x120:
121 case 0x128:
122 case 0x130:
123 case 0x138:
124 case 0x140:
125 case 0x148:
126 case 0x150:
127 case 0x158:
128 case 0x160:
129 case 0x168:
130 case 0x170:
131 case 0x178:
132 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
133 break;
134 case 0x180:
135 case 0x188:
136 case 0x190:
137 case 0x198:
138 case 0x1A0:
139 case 0x1A8:
140 case 0x1B0:
141 case 0x1B8:
142 case 0x1C0:
143 case 0x1C8:
144 case 0x1D0:
145 case 0x1D8:
146 case 0x1E0:
147 case 0x1E8:
148 case 0x1F0:
149 case 0x1F8:
150 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
151 break;
152 case 0x200:
153 case 0x208:
154 case 0x210:
155 case 0x218:
156 case 0x220:
157 case 0x228:
158 case 0x230:
159 case 0x238:
160 case 0x240:
161 case 0x248:
162 case 0x250:
163 case 0x258:
164 case 0x260:
165 case 0x268:
166 case 0x270:
167 case 0x278:
168 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
169 break;
170 case 0x280:
171 regNum = APIC_ERROR_STATUS;
172 break;
173 case 0x300:
174 regNum = APIC_INTERRUPT_COMMAND_LOW;
175 break;
176 case 0x310:
177 regNum = APIC_INTERRUPT_COMMAND_HIGH;
178 break;
179 case 0x320:
180 regNum = APIC_LVT_TIMER;
181 break;
182 case 0x330:
183 regNum = APIC_LVT_THERMAL_SENSOR;
184 break;
185 case 0x340:
186 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
187 break;
188 case 0x350:
189 regNum = APIC_LVT_LINT0;
190 break;
191 case 0x360:
192 regNum = APIC_LVT_LINT1;
193 break;
194 case 0x370:
195 regNum = APIC_LVT_ERROR;
196 break;
197 case 0x380:
198 regNum = APIC_INITIAL_COUNT;
199 break;
200 case 0x390:
201 regNum = APIC_CURRENT_COUNT;
202 break;
203 case 0x3E0:
204 regNum = APIC_DIVIDE_CONFIGURATION;
205 break;
206 default:
207 // A reserved register field.
208 panic("Accessed reserved register field %#x.\n", paddr);
209 break;
210 }
211 return regNum;
212}
213}
214
215Tick
216X86ISA::Interrupts::read(PacketPtr pkt)
217{
218 Addr offset = pkt->getAddr() - pioAddr;
219 //Make sure we're at least only accessing one register.
220 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
221 panic("Accessed more than one register at a time in the APIC!\n");
222 ApicRegIndex reg = decodeAddr(offset);
223 uint32_t val = htog(readReg(reg));
224 DPRINTF(LocalApic,
225 "Reading Local APIC register %d at offset %#x as %#x.\n",
226 reg, offset, val);
227 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
228 pkt->makeAtomicResponse();
229 return latency;
230}
231
232Tick
233X86ISA::Interrupts::write(PacketPtr pkt)
234{
235 Addr offset = pkt->getAddr() - pioAddr;
236 //Make sure we're at least only accessing one register.
237 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
238 panic("Accessed more than one register at a time in the APIC!\n");
239 ApicRegIndex reg = decodeAddr(offset);
240 uint32_t val = regs[reg];
241 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
242 DPRINTF(LocalApic,
243 "Writing Local APIC register %d at offset %#x as %#x.\n",
244 reg, offset, gtoh(val));
245 setReg(reg, gtoh(val));
246 pkt->makeAtomicResponse();
247 return latency;
248}
249void
250X86ISA::Interrupts::requestInterrupt(uint8_t vector,
251 uint8_t deliveryMode, bool level)
252{
253 /*
254 * Fixed and lowest-priority delivery mode interrupts are handled
255 * using the IRR/ISR registers, checking against the TPR, etc.
256 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
257 */
258 if (deliveryMode == DeliveryMode::Fixed ||
259 deliveryMode == DeliveryMode::LowestPriority) {
260 DPRINTF(LocalApic, "Interrupt is an %s.\n",
261 DeliveryMode::names[deliveryMode]);
262 // Queue up the interrupt in the IRR.
263 if (vector > IRRV)
264 IRRV = vector;
265 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
266 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
267 if (level) {
268 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
269 } else {
270 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
271 }
272 }
273 } else if (!DeliveryMode::isReserved(deliveryMode)) {
274 DPRINTF(LocalApic, "Interrupt is an %s.\n",
275 DeliveryMode::names[deliveryMode]);
276 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
277 pendingUnmaskableInt = pendingSmi = true;
278 smiVector = vector;
279 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
280 pendingUnmaskableInt = pendingNmi = true;
281 nmiVector = vector;
282 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
283 pendingExtInt = true;
284 extIntVector = vector;
285 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
286 pendingUnmaskableInt = pendingInit = true;
287 initVector = vector;
288 } else if (deliveryMode == DeliveryMode::SIPI &&
289 !pendingStartup && !startedUp) {
290 pendingUnmaskableInt = pendingStartup = true;
291 startupVector = vector;
292 }
293 }
294 cpu->wakeup();
295}
296
297
298void
299X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
300{
301 assert(newCPU);
302 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
303 panic("Local APICs can't be moved between CPUs"
304 " with different IDs.\n");
305 }
306 cpu = newCPU;
307 initialApicId = cpu->cpuId();
308 regs[APIC_ID] = (initialApicId << 24);
309}
310
311
312void
313X86ISA::Interrupts::init()
314{
315 BasicPioDevice::init();
316 Pc * pc = dynamic_cast<Pc *>(platform);
317 assert(pc);
318 pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
319}
320
321
322Tick
323X86ISA::Interrupts::recvMessage(PacketPtr pkt)
324{
325 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
326 assert(pkt->cmd == MemCmd::MessageReq);
327 switch(offset)
328 {
329 case 0:
330 {
331 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
332 DPRINTF(LocalApic,
333 "Got Trigger Interrupt message with vector %#x.\n",
334 message.vector);
335
336 requestInterrupt(message.vector,
337 message.deliveryMode, message.trigger);
338 }
339 break;
340 default:
341 panic("Local apic got unknown interrupt message at offset %#x.\n",
342 offset);
343 break;
344 }
345 pkt->makeAtomicResponse();
346 return latency;
347}
348
349
350Tick
351X86ISA::Interrupts::recvResponse(PacketPtr pkt)
352{
353 assert(!pkt->isError());
354 assert(pkt->cmd == MemCmd::MessageResp);
355 if (--pendingIPIs == 0) {
356 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
357 // Record that the ICR is now idle.
358 low.deliveryStatus = 0;
359 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
360 }
361 delete pkt->req;
362 delete pkt;
363 DPRINTF(LocalApic, "ICR is now idle.\n");
364 return 0;
365}
366
367
368void
369X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
370{
371 range_list.clear();
372 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
373 x86LocalAPICAddress(initialApicId, 0) +
374 PageBytes);
375 range_list.push_back(range);
376 pioAddr = range.start;
377}
378
379
380void
381X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
382{
383 range_list.clear();
384 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
385 x86InterruptAddress(initialApicId, 0) +
386 PhysAddrAPICRangeSize));
387}
388
389
390uint32_t
391X86ISA::Interrupts::readReg(ApicRegIndex reg)
392{
393 if (reg >= APIC_TRIGGER_MODE(0) &&
394 reg <= APIC_TRIGGER_MODE(15)) {
395 panic("Local APIC Trigger Mode registers are unimplemented.\n");
396 }
397 switch (reg) {
398 case APIC_ARBITRATION_PRIORITY:
399 panic("Local APIC Arbitration Priority register unimplemented.\n");
400 break;
401 case APIC_PROCESSOR_PRIORITY:
402 panic("Local APIC Processor Priority register unimplemented.\n");
403 break;
404 case APIC_ERROR_STATUS:
405 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
406 break;
407 case APIC_CURRENT_COUNT:
408 {
409 if (apicTimerEvent.scheduled()) {
410 assert(clock);
411 // Compute how many m5 ticks happen per count.
412 uint64_t ticksPerCount = clock *
413 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
414 // Compute how many m5 ticks are left.
415 uint64_t val = apicTimerEvent.when() - curTick;
416 // Turn that into a count.
417 val = (val + ticksPerCount - 1) / ticksPerCount;
418 return val;
419 } else {
420 return 0;
421 }
422 }
423 default:
424 break;
425 }
426 return regs[reg];
427}
428
429void
430X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
431{
432 uint32_t newVal = val;
433 if (reg >= APIC_IN_SERVICE(0) &&
434 reg <= APIC_IN_SERVICE(15)) {
435 panic("Local APIC In-Service registers are unimplemented.\n");
436 }
437 if (reg >= APIC_TRIGGER_MODE(0) &&
438 reg <= APIC_TRIGGER_MODE(15)) {
439 panic("Local APIC Trigger Mode registers are unimplemented.\n");
440 }
441 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
442 reg <= APIC_INTERRUPT_REQUEST(15)) {
443 panic("Local APIC Interrupt Request registers "
444 "are unimplemented.\n");
445 }
446 switch (reg) {
447 case APIC_ID:
448 newVal = val & 0xFF;
449 break;
450 case APIC_VERSION:
451 // The Local APIC Version register is read only.
452 return;
453 case APIC_TASK_PRIORITY:
454 newVal = val & 0xFF;
455 break;
456 case APIC_ARBITRATION_PRIORITY:
457 panic("Local APIC Arbitration Priority register unimplemented.\n");
458 break;
459 case APIC_PROCESSOR_PRIORITY:
460 panic("Local APIC Processor Priority register unimplemented.\n");
461 break;
462 case APIC_EOI:
463 // Remove the interrupt that just completed from the local apic state.
464 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
465 updateISRV();
466 return;
467 case APIC_LOGICAL_DESTINATION:
468 newVal = val & 0xFF000000;
469 break;
470 case APIC_DESTINATION_FORMAT:
471 newVal = val | 0x0FFFFFFF;
472 break;
473 case APIC_SPURIOUS_INTERRUPT_VECTOR:
474 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
475 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
476 if (val & (1 << 9))
477 warn("Focus processor checking not implemented.\n");
478 break;
479 case APIC_ERROR_STATUS:
480 {
481 if (regs[APIC_INTERNAL_STATE] & 0x1) {
482 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
483 newVal = 0;
484 } else {
485 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
486 return;
487 }
488
489 }
490 break;
491 case APIC_INTERRUPT_COMMAND_LOW:
492 {
493 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
494 // Check if we're already sending an IPI.
495 if (low.deliveryStatus) {
496 newVal = low;
497 break;
498 }
499 low = val;
500 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
501 // Record that an IPI is being sent.
502 low.deliveryStatus = 1;
503 TriggerIntMessage message;
504 message.destination = high.destination;
505 message.vector = low.vector;
506 message.deliveryMode = low.deliveryMode;
507 message.destMode = low.destMode;
508 message.level = low.level;
509 message.trigger = low.trigger;
510 bool timing = sys->getMemoryMode() == Enums::timing;
511 // Be careful no updates of the delivery status bit get lost.
512 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "dev/x86/i82094aa.hh"
63#include "dev/x86/pc.hh"
64#include "dev/x86/south_bridge.hh"
65#include "mem/packet_access.hh"
66#include "sim/system.hh"
67
68int
69divideFromConf(uint32_t conf)
70{
71 // This figures out what division we want from the division configuration
72 // register in the local APIC. The encoding is a little odd but it can
73 // be deciphered fairly easily.
74 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
75 shift = (shift + 1) % 8;
76 return 1 << shift;
77}
78
79namespace X86ISA
80{
81
82ApicRegIndex
83decodeAddr(Addr paddr)
84{
85 ApicRegIndex regNum;
86 paddr &= ~mask(3);
87 switch (paddr)
88 {
89 case 0x20:
90 regNum = APIC_ID;
91 break;
92 case 0x30:
93 regNum = APIC_VERSION;
94 break;
95 case 0x80:
96 regNum = APIC_TASK_PRIORITY;
97 break;
98 case 0x90:
99 regNum = APIC_ARBITRATION_PRIORITY;
100 break;
101 case 0xA0:
102 regNum = APIC_PROCESSOR_PRIORITY;
103 break;
104 case 0xB0:
105 regNum = APIC_EOI;
106 break;
107 case 0xD0:
108 regNum = APIC_LOGICAL_DESTINATION;
109 break;
110 case 0xE0:
111 regNum = APIC_DESTINATION_FORMAT;
112 break;
113 case 0xF0:
114 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
115 break;
116 case 0x100:
117 case 0x108:
118 case 0x110:
119 case 0x118:
120 case 0x120:
121 case 0x128:
122 case 0x130:
123 case 0x138:
124 case 0x140:
125 case 0x148:
126 case 0x150:
127 case 0x158:
128 case 0x160:
129 case 0x168:
130 case 0x170:
131 case 0x178:
132 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
133 break;
134 case 0x180:
135 case 0x188:
136 case 0x190:
137 case 0x198:
138 case 0x1A0:
139 case 0x1A8:
140 case 0x1B0:
141 case 0x1B8:
142 case 0x1C0:
143 case 0x1C8:
144 case 0x1D0:
145 case 0x1D8:
146 case 0x1E0:
147 case 0x1E8:
148 case 0x1F0:
149 case 0x1F8:
150 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
151 break;
152 case 0x200:
153 case 0x208:
154 case 0x210:
155 case 0x218:
156 case 0x220:
157 case 0x228:
158 case 0x230:
159 case 0x238:
160 case 0x240:
161 case 0x248:
162 case 0x250:
163 case 0x258:
164 case 0x260:
165 case 0x268:
166 case 0x270:
167 case 0x278:
168 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
169 break;
170 case 0x280:
171 regNum = APIC_ERROR_STATUS;
172 break;
173 case 0x300:
174 regNum = APIC_INTERRUPT_COMMAND_LOW;
175 break;
176 case 0x310:
177 regNum = APIC_INTERRUPT_COMMAND_HIGH;
178 break;
179 case 0x320:
180 regNum = APIC_LVT_TIMER;
181 break;
182 case 0x330:
183 regNum = APIC_LVT_THERMAL_SENSOR;
184 break;
185 case 0x340:
186 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
187 break;
188 case 0x350:
189 regNum = APIC_LVT_LINT0;
190 break;
191 case 0x360:
192 regNum = APIC_LVT_LINT1;
193 break;
194 case 0x370:
195 regNum = APIC_LVT_ERROR;
196 break;
197 case 0x380:
198 regNum = APIC_INITIAL_COUNT;
199 break;
200 case 0x390:
201 regNum = APIC_CURRENT_COUNT;
202 break;
203 case 0x3E0:
204 regNum = APIC_DIVIDE_CONFIGURATION;
205 break;
206 default:
207 // A reserved register field.
208 panic("Accessed reserved register field %#x.\n", paddr);
209 break;
210 }
211 return regNum;
212}
213}
214
215Tick
216X86ISA::Interrupts::read(PacketPtr pkt)
217{
218 Addr offset = pkt->getAddr() - pioAddr;
219 //Make sure we're at least only accessing one register.
220 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
221 panic("Accessed more than one register at a time in the APIC!\n");
222 ApicRegIndex reg = decodeAddr(offset);
223 uint32_t val = htog(readReg(reg));
224 DPRINTF(LocalApic,
225 "Reading Local APIC register %d at offset %#x as %#x.\n",
226 reg, offset, val);
227 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
228 pkt->makeAtomicResponse();
229 return latency;
230}
231
232Tick
233X86ISA::Interrupts::write(PacketPtr pkt)
234{
235 Addr offset = pkt->getAddr() - pioAddr;
236 //Make sure we're at least only accessing one register.
237 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
238 panic("Accessed more than one register at a time in the APIC!\n");
239 ApicRegIndex reg = decodeAddr(offset);
240 uint32_t val = regs[reg];
241 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
242 DPRINTF(LocalApic,
243 "Writing Local APIC register %d at offset %#x as %#x.\n",
244 reg, offset, gtoh(val));
245 setReg(reg, gtoh(val));
246 pkt->makeAtomicResponse();
247 return latency;
248}
249void
250X86ISA::Interrupts::requestInterrupt(uint8_t vector,
251 uint8_t deliveryMode, bool level)
252{
253 /*
254 * Fixed and lowest-priority delivery mode interrupts are handled
255 * using the IRR/ISR registers, checking against the TPR, etc.
256 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
257 */
258 if (deliveryMode == DeliveryMode::Fixed ||
259 deliveryMode == DeliveryMode::LowestPriority) {
260 DPRINTF(LocalApic, "Interrupt is an %s.\n",
261 DeliveryMode::names[deliveryMode]);
262 // Queue up the interrupt in the IRR.
263 if (vector > IRRV)
264 IRRV = vector;
265 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
266 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
267 if (level) {
268 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
269 } else {
270 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
271 }
272 }
273 } else if (!DeliveryMode::isReserved(deliveryMode)) {
274 DPRINTF(LocalApic, "Interrupt is an %s.\n",
275 DeliveryMode::names[deliveryMode]);
276 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
277 pendingUnmaskableInt = pendingSmi = true;
278 smiVector = vector;
279 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
280 pendingUnmaskableInt = pendingNmi = true;
281 nmiVector = vector;
282 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
283 pendingExtInt = true;
284 extIntVector = vector;
285 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
286 pendingUnmaskableInt = pendingInit = true;
287 initVector = vector;
288 } else if (deliveryMode == DeliveryMode::SIPI &&
289 !pendingStartup && !startedUp) {
290 pendingUnmaskableInt = pendingStartup = true;
291 startupVector = vector;
292 }
293 }
294 cpu->wakeup();
295}
296
297
298void
299X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
300{
301 assert(newCPU);
302 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
303 panic("Local APICs can't be moved between CPUs"
304 " with different IDs.\n");
305 }
306 cpu = newCPU;
307 initialApicId = cpu->cpuId();
308 regs[APIC_ID] = (initialApicId << 24);
309}
310
311
312void
313X86ISA::Interrupts::init()
314{
315 BasicPioDevice::init();
316 Pc * pc = dynamic_cast<Pc *>(platform);
317 assert(pc);
318 pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
319}
320
321
322Tick
323X86ISA::Interrupts::recvMessage(PacketPtr pkt)
324{
325 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
326 assert(pkt->cmd == MemCmd::MessageReq);
327 switch(offset)
328 {
329 case 0:
330 {
331 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
332 DPRINTF(LocalApic,
333 "Got Trigger Interrupt message with vector %#x.\n",
334 message.vector);
335
336 requestInterrupt(message.vector,
337 message.deliveryMode, message.trigger);
338 }
339 break;
340 default:
341 panic("Local apic got unknown interrupt message at offset %#x.\n",
342 offset);
343 break;
344 }
345 pkt->makeAtomicResponse();
346 return latency;
347}
348
349
350Tick
351X86ISA::Interrupts::recvResponse(PacketPtr pkt)
352{
353 assert(!pkt->isError());
354 assert(pkt->cmd == MemCmd::MessageResp);
355 if (--pendingIPIs == 0) {
356 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
357 // Record that the ICR is now idle.
358 low.deliveryStatus = 0;
359 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
360 }
361 delete pkt->req;
362 delete pkt;
363 DPRINTF(LocalApic, "ICR is now idle.\n");
364 return 0;
365}
366
367
368void
369X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
370{
371 range_list.clear();
372 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
373 x86LocalAPICAddress(initialApicId, 0) +
374 PageBytes);
375 range_list.push_back(range);
376 pioAddr = range.start;
377}
378
379
380void
381X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
382{
383 range_list.clear();
384 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
385 x86InterruptAddress(initialApicId, 0) +
386 PhysAddrAPICRangeSize));
387}
388
389
390uint32_t
391X86ISA::Interrupts::readReg(ApicRegIndex reg)
392{
393 if (reg >= APIC_TRIGGER_MODE(0) &&
394 reg <= APIC_TRIGGER_MODE(15)) {
395 panic("Local APIC Trigger Mode registers are unimplemented.\n");
396 }
397 switch (reg) {
398 case APIC_ARBITRATION_PRIORITY:
399 panic("Local APIC Arbitration Priority register unimplemented.\n");
400 break;
401 case APIC_PROCESSOR_PRIORITY:
402 panic("Local APIC Processor Priority register unimplemented.\n");
403 break;
404 case APIC_ERROR_STATUS:
405 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
406 break;
407 case APIC_CURRENT_COUNT:
408 {
409 if (apicTimerEvent.scheduled()) {
410 assert(clock);
411 // Compute how many m5 ticks happen per count.
412 uint64_t ticksPerCount = clock *
413 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
414 // Compute how many m5 ticks are left.
415 uint64_t val = apicTimerEvent.when() - curTick;
416 // Turn that into a count.
417 val = (val + ticksPerCount - 1) / ticksPerCount;
418 return val;
419 } else {
420 return 0;
421 }
422 }
423 default:
424 break;
425 }
426 return regs[reg];
427}
428
429void
430X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
431{
432 uint32_t newVal = val;
433 if (reg >= APIC_IN_SERVICE(0) &&
434 reg <= APIC_IN_SERVICE(15)) {
435 panic("Local APIC In-Service registers are unimplemented.\n");
436 }
437 if (reg >= APIC_TRIGGER_MODE(0) &&
438 reg <= APIC_TRIGGER_MODE(15)) {
439 panic("Local APIC Trigger Mode registers are unimplemented.\n");
440 }
441 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
442 reg <= APIC_INTERRUPT_REQUEST(15)) {
443 panic("Local APIC Interrupt Request registers "
444 "are unimplemented.\n");
445 }
446 switch (reg) {
447 case APIC_ID:
448 newVal = val & 0xFF;
449 break;
450 case APIC_VERSION:
451 // The Local APIC Version register is read only.
452 return;
453 case APIC_TASK_PRIORITY:
454 newVal = val & 0xFF;
455 break;
456 case APIC_ARBITRATION_PRIORITY:
457 panic("Local APIC Arbitration Priority register unimplemented.\n");
458 break;
459 case APIC_PROCESSOR_PRIORITY:
460 panic("Local APIC Processor Priority register unimplemented.\n");
461 break;
462 case APIC_EOI:
463 // Remove the interrupt that just completed from the local apic state.
464 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
465 updateISRV();
466 return;
467 case APIC_LOGICAL_DESTINATION:
468 newVal = val & 0xFF000000;
469 break;
470 case APIC_DESTINATION_FORMAT:
471 newVal = val | 0x0FFFFFFF;
472 break;
473 case APIC_SPURIOUS_INTERRUPT_VECTOR:
474 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
475 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
476 if (val & (1 << 9))
477 warn("Focus processor checking not implemented.\n");
478 break;
479 case APIC_ERROR_STATUS:
480 {
481 if (regs[APIC_INTERNAL_STATE] & 0x1) {
482 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
483 newVal = 0;
484 } else {
485 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
486 return;
487 }
488
489 }
490 break;
491 case APIC_INTERRUPT_COMMAND_LOW:
492 {
493 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
494 // Check if we're already sending an IPI.
495 if (low.deliveryStatus) {
496 newVal = low;
497 break;
498 }
499 low = val;
500 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
501 // Record that an IPI is being sent.
502 low.deliveryStatus = 1;
503 TriggerIntMessage message;
504 message.destination = high.destination;
505 message.vector = low.vector;
506 message.deliveryMode = low.deliveryMode;
507 message.destMode = low.destMode;
508 message.level = low.level;
509 message.trigger = low.trigger;
510 bool timing = sys->getMemoryMode() == Enums::timing;
511 // Be careful no updates of the delivery status bit get lost.
512 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
|
| 513 ApicList apics;
514 int numContexts = sys->numContexts();
|
513 switch (low.destShorthand) {
514 case 0:
| 515 switch (low.destShorthand) {
516 case 0:
|
515 pendingIPIs++;
516 intPort->sendMessage(message, timing);
517 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
| 517 if (message.deliveryMode == DeliveryMode::LowestPriority) {
518 panic("Lowest priority delivery mode "
519 "IPIs aren't implemented.\n");
520 }
521 if (message.destMode == 1) {
522 int dest = message.destination;
523 hack_once("Assuming logical destinations are 1 << id.\n");
524 for (int i = 0; i < numContexts; i++) {
525 if (dest & 0x1)
526 apics.push_back(i);
527 dest = dest >> 1;
528 }
529 } else {
530 if (message.destination == 0xFF) {
531 for (int i = 0; i < numContexts; i++) {
532 if (i == initialApicId) {
533 requestInterrupt(message.vector,
534 message.deliveryMode, message.trigger);
535 } else {
536 apics.push_back(i);
537 }
538 }
539 } else {
540 if (message.destination == initialApicId) {
541 requestInterrupt(message.vector,
542 message.deliveryMode, message.trigger);
543 } else {
544 apics.push_back(message.destination);
545 }
546 }
547 }
|
518 break;
519 case 1:
520 newVal = val;
521 requestInterrupt(message.vector,
522 message.deliveryMode, message.trigger);
523 break;
524 case 2:
525 requestInterrupt(message.vector,
526 message.deliveryMode, message.trigger);
527 // Fall through
528 case 3:
529 {
| 548 break;
549 case 1:
550 newVal = val;
551 requestInterrupt(message.vector,
552 message.deliveryMode, message.trigger);
553 break;
554 case 2:
555 requestInterrupt(message.vector,
556 message.deliveryMode, message.trigger);
557 // Fall through
558 case 3:
559 {
|
530 int numContexts = sys->numContexts();
531 pendingIPIs += (numContexts - 1);
| |
532 for (int i = 0; i < numContexts; i++) {
| 560 for (int i = 0; i < numContexts; i++) {
|
533 int thisId = sys->getThreadContext(i)->contextId();
534 if (thisId != initialApicId) {
535 PacketPtr pkt = buildIntRequest(thisId, message);
536 if (timing)
537 intPort->sendMessageTiming(pkt, latency);
538 else
539 intPort->sendMessageAtomic(pkt);
| 561 if (i != initialApicId) {
562 apics.push_back(i);
|
540 }
541 }
542 }
| 563 }
564 }
565 }
|
543 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
| |
544 break;
545 }
| 566 break;
567 }
|
| 568 pendingIPIs += apics.size();
569 intPort->sendMessage(apics, message, timing);
570 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
|
546 }
547 break;
548 case APIC_LVT_TIMER:
549 case APIC_LVT_THERMAL_SENSOR:
550 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
551 case APIC_LVT_LINT0:
552 case APIC_LVT_LINT1:
553 case APIC_LVT_ERROR:
554 {
555 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
556 newVal = (val & ~readOnlyMask) |
557 (regs[reg] & readOnlyMask);
558 }
559 break;
560 case APIC_INITIAL_COUNT:
561 {
562 assert(clock);
563 newVal = bits(val, 31, 0);
564 // Compute how many timer ticks we're being programmed for.
565 uint64_t newCount = newVal *
566 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
567 // Schedule on the edge of the next tick plus the new count.
568 Tick offset = curTick % clock;
569 if (offset) {
570 reschedule(apicTimerEvent,
571 curTick + (newCount + 1) * clock - offset, true);
572 } else {
573 reschedule(apicTimerEvent,
574 curTick + newCount * clock, true);
575 }
576 }
577 break;
578 case APIC_CURRENT_COUNT:
579 //Local APIC Current Count register is read only.
580 return;
581 case APIC_DIVIDE_CONFIGURATION:
582 newVal = val & 0xB;
583 break;
584 default:
585 break;
586 }
587 regs[reg] = newVal;
588 return;
589}
590
591
592X86ISA::Interrupts::Interrupts(Params * p) :
593 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
594 apicTimerEvent(this),
595 pendingSmi(false), smiVector(0),
596 pendingNmi(false), nmiVector(0),
597 pendingExtInt(false), extIntVector(0),
598 pendingInit(false), initVector(0),
599 pendingStartup(false), startupVector(0),
600 startedUp(false), pendingUnmaskableInt(false),
601 pendingIPIs(0), cpu(NULL)
602{
603 pioSize = PageBytes;
604 memset(regs, 0, sizeof(regs));
605 //Set the local apic DFR to the flat model.
606 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
607 ISRV = 0;
608 IRRV = 0;
609}
610
611
612bool
613X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
614{
615 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
616 if (pendingUnmaskableInt) {
617 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
618 return true;
619 }
620 if (rflags.intf) {
621 if (pendingExtInt) {
622 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
623 return true;
624 }
625 if (IRRV > ISRV && bits(IRRV, 7, 4) >
626 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
627 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
628 return true;
629 }
630 }
631 return false;
632}
633
634Fault
635X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
636{
637 assert(checkInterrupts(tc));
638 // These are all probably fairly uncommon, so we'll make them easier to
639 // check for.
640 if (pendingUnmaskableInt) {
641 if (pendingSmi) {
642 DPRINTF(LocalApic, "Generated SMI fault object.\n");
643 return new SystemManagementInterrupt();
644 } else if (pendingNmi) {
645 DPRINTF(LocalApic, "Generated NMI fault object.\n");
646 return new NonMaskableInterrupt(nmiVector);
647 } else if (pendingInit) {
648 DPRINTF(LocalApic, "Generated INIT fault object.\n");
649 return new InitInterrupt(initVector);
650 } else if (pendingStartup) {
651 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
652 return new StartupInterrupt(startupVector);
653 } else {
654 panic("pendingUnmaskableInt set, but no unmaskable "
655 "ints were pending.\n");
656 return NoFault;
657 }
658 } else if (pendingExtInt) {
659 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
660 return new ExternalInterrupt(extIntVector);
661 } else {
662 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
663 // The only thing left are fixed and lowest priority interrupts.
664 return new ExternalInterrupt(IRRV);
665 }
666}
667
668void
669X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
670{
671 assert(checkInterrupts(tc));
672 if (pendingUnmaskableInt) {
673 if (pendingSmi) {
674 DPRINTF(LocalApic, "SMI sent to core.\n");
675 pendingSmi = false;
676 } else if (pendingNmi) {
677 DPRINTF(LocalApic, "NMI sent to core.\n");
678 pendingNmi = false;
679 } else if (pendingInit) {
680 DPRINTF(LocalApic, "Init sent to core.\n");
681 pendingInit = false;
682 startedUp = false;
683 } else if (pendingStartup) {
684 DPRINTF(LocalApic, "SIPI sent to core.\n");
685 pendingStartup = false;
686 startedUp = true;
687 }
688 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
689 pendingUnmaskableInt = false;
690 } else if (pendingExtInt) {
691 pendingExtInt = false;
692 } else {
693 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
694 // Mark the interrupt as "in service".
695 ISRV = IRRV;
696 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
697 // Clear it out of the IRR.
698 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
699 updateIRRV();
700 }
701}
702
703X86ISA::Interrupts *
704X86LocalApicParams::create()
705{
706 return new X86ISA::Interrupts(this);
707}
| 571 }
572 break;
573 case APIC_LVT_TIMER:
574 case APIC_LVT_THERMAL_SENSOR:
575 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
576 case APIC_LVT_LINT0:
577 case APIC_LVT_LINT1:
578 case APIC_LVT_ERROR:
579 {
580 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
581 newVal = (val & ~readOnlyMask) |
582 (regs[reg] & readOnlyMask);
583 }
584 break;
585 case APIC_INITIAL_COUNT:
586 {
587 assert(clock);
588 newVal = bits(val, 31, 0);
589 // Compute how many timer ticks we're being programmed for.
590 uint64_t newCount = newVal *
591 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
592 // Schedule on the edge of the next tick plus the new count.
593 Tick offset = curTick % clock;
594 if (offset) {
595 reschedule(apicTimerEvent,
596 curTick + (newCount + 1) * clock - offset, true);
597 } else {
598 reschedule(apicTimerEvent,
599 curTick + newCount * clock, true);
600 }
601 }
602 break;
603 case APIC_CURRENT_COUNT:
604 //Local APIC Current Count register is read only.
605 return;
606 case APIC_DIVIDE_CONFIGURATION:
607 newVal = val & 0xB;
608 break;
609 default:
610 break;
611 }
612 regs[reg] = newVal;
613 return;
614}
615
616
617X86ISA::Interrupts::Interrupts(Params * p) :
618 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
619 apicTimerEvent(this),
620 pendingSmi(false), smiVector(0),
621 pendingNmi(false), nmiVector(0),
622 pendingExtInt(false), extIntVector(0),
623 pendingInit(false), initVector(0),
624 pendingStartup(false), startupVector(0),
625 startedUp(false), pendingUnmaskableInt(false),
626 pendingIPIs(0), cpu(NULL)
627{
628 pioSize = PageBytes;
629 memset(regs, 0, sizeof(regs));
630 //Set the local apic DFR to the flat model.
631 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
632 ISRV = 0;
633 IRRV = 0;
634}
635
636
637bool
638X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
639{
640 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
641 if (pendingUnmaskableInt) {
642 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
643 return true;
644 }
645 if (rflags.intf) {
646 if (pendingExtInt) {
647 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
648 return true;
649 }
650 if (IRRV > ISRV && bits(IRRV, 7, 4) >
651 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
652 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
653 return true;
654 }
655 }
656 return false;
657}
658
659Fault
660X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
661{
662 assert(checkInterrupts(tc));
663 // These are all probably fairly uncommon, so we'll make them easier to
664 // check for.
665 if (pendingUnmaskableInt) {
666 if (pendingSmi) {
667 DPRINTF(LocalApic, "Generated SMI fault object.\n");
668 return new SystemManagementInterrupt();
669 } else if (pendingNmi) {
670 DPRINTF(LocalApic, "Generated NMI fault object.\n");
671 return new NonMaskableInterrupt(nmiVector);
672 } else if (pendingInit) {
673 DPRINTF(LocalApic, "Generated INIT fault object.\n");
674 return new InitInterrupt(initVector);
675 } else if (pendingStartup) {
676 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
677 return new StartupInterrupt(startupVector);
678 } else {
679 panic("pendingUnmaskableInt set, but no unmaskable "
680 "ints were pending.\n");
681 return NoFault;
682 }
683 } else if (pendingExtInt) {
684 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
685 return new ExternalInterrupt(extIntVector);
686 } else {
687 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
688 // The only thing left are fixed and lowest priority interrupts.
689 return new ExternalInterrupt(IRRV);
690 }
691}
692
693void
694X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
695{
696 assert(checkInterrupts(tc));
697 if (pendingUnmaskableInt) {
698 if (pendingSmi) {
699 DPRINTF(LocalApic, "SMI sent to core.\n");
700 pendingSmi = false;
701 } else if (pendingNmi) {
702 DPRINTF(LocalApic, "NMI sent to core.\n");
703 pendingNmi = false;
704 } else if (pendingInit) {
705 DPRINTF(LocalApic, "Init sent to core.\n");
706 pendingInit = false;
707 startedUp = false;
708 } else if (pendingStartup) {
709 DPRINTF(LocalApic, "SIPI sent to core.\n");
710 pendingStartup = false;
711 startedUp = true;
712 }
713 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
714 pendingUnmaskableInt = false;
715 } else if (pendingExtInt) {
716 pendingExtInt = false;
717 } else {
718 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
719 // Mark the interrupt as "in service".
720 ISRV = IRRV;
721 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
722 // Clear it out of the IRR.
723 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
724 updateIRRV();
725 }
726}
727
728X86ISA::Interrupts *
729X86LocalApicParams::create()
730{
731 return new X86ISA::Interrupts(this);
732}
|