1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
64
65int
66divideFromConf(uint32_t conf)
67{
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
72 shift = (shift + 1) % 8;
73 return 1 << shift;
74}
75
76namespace X86ISA
77{
78
79ApicRegIndex
80decodeAddr(Addr paddr)
81{
82 ApicRegIndex regNum;
83 paddr &= ~mask(3);
84 switch (paddr)
85 {
86 case 0x20:
87 regNum = APIC_ID;
88 break;
89 case 0x30:
90 regNum = APIC_VERSION;
91 break;
92 case 0x80:
93 regNum = APIC_TASK_PRIORITY;
94 break;
95 case 0x90:
96 regNum = APIC_ARBITRATION_PRIORITY;
97 break;
98 case 0xA0:
99 regNum = APIC_PROCESSOR_PRIORITY;
100 break;
101 case 0xB0:
102 regNum = APIC_EOI;
103 break;
104 case 0xD0:
105 regNum = APIC_LOGICAL_DESTINATION;
106 break;
107 case 0xE0:
108 regNum = APIC_DESTINATION_FORMAT;
109 break;
110 case 0xF0:
111 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
112 break;
113 case 0x100:
114 case 0x108:
115 case 0x110:
116 case 0x118:
117 case 0x120:
118 case 0x128:
119 case 0x130:
120 case 0x138:
121 case 0x140:
122 case 0x148:
123 case 0x150:
124 case 0x158:
125 case 0x160:
126 case 0x168:
127 case 0x170:
128 case 0x178:
129 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
130 break;
131 case 0x180:
132 case 0x188:
133 case 0x190:
134 case 0x198:
135 case 0x1A0:
136 case 0x1A8:
137 case 0x1B0:
138 case 0x1B8:
139 case 0x1C0:
140 case 0x1C8:
141 case 0x1D0:
142 case 0x1D8:
143 case 0x1E0:
144 case 0x1E8:
145 case 0x1F0:
146 case 0x1F8:
147 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
148 break;
149 case 0x200:
150 case 0x208:
151 case 0x210:
152 case 0x218:
153 case 0x220:
154 case 0x228:
155 case 0x230:
156 case 0x238:
157 case 0x240:
158 case 0x248:
159 case 0x250:
160 case 0x258:
161 case 0x260:
162 case 0x268:
163 case 0x270:
164 case 0x278:
165 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
166 break;
167 case 0x280:
168 regNum = APIC_ERROR_STATUS;
169 break;
170 case 0x300:
171 regNum = APIC_INTERRUPT_COMMAND_LOW;
172 break;
173 case 0x310:
174 regNum = APIC_INTERRUPT_COMMAND_HIGH;
175 break;
176 case 0x320:
177 regNum = APIC_LVT_TIMER;
178 break;
179 case 0x330:
180 regNum = APIC_LVT_THERMAL_SENSOR;
181 break;
182 case 0x340:
183 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
184 break;
185 case 0x350:
186 regNum = APIC_LVT_LINT0;
187 break;
188 case 0x360:
189 regNum = APIC_LVT_LINT1;
190 break;
191 case 0x370:
192 regNum = APIC_LVT_ERROR;
193 break;
194 case 0x380:
195 regNum = APIC_INITIAL_COUNT;
196 break;
197 case 0x390:
198 regNum = APIC_CURRENT_COUNT;
199 break;
200 case 0x3E0:
201 regNum = APIC_DIVIDE_CONFIGURATION;
202 break;
203 default:
204 // A reserved register field.
205 panic("Accessed reserved register field %#x.\n", paddr);
206 break;
207 }
208 return regNum;
209}
210}
211
212Tick
213X86ISA::Interrupts::read(PacketPtr pkt)
214{
215 Addr offset = pkt->getAddr() - pioAddr;
216 //Make sure we're at least only accessing one register.
217 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
218 panic("Accessed more than one register at a time in the APIC!\n");
219 ApicRegIndex reg = decodeAddr(offset);
220 uint32_t val = htog(readReg(reg));
221 DPRINTF(LocalApic,
222 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 reg, offset, val);
224 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
225 pkt->makeAtomicResponse();
226 return latency;
227}
228
229Tick
230X86ISA::Interrupts::write(PacketPtr pkt)
231{
232 Addr offset = pkt->getAddr() - pioAddr;
233 //Make sure we're at least only accessing one register.
234 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
235 panic("Accessed more than one register at a time in the APIC!\n");
236 ApicRegIndex reg = decodeAddr(offset);
237 uint32_t val = regs[reg];
238 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
239 DPRINTF(LocalApic,
240 "Writing Local APIC register %d at offset %#x as %#x.\n",
241 reg, offset, gtoh(val));
242 setReg(reg, gtoh(val));
243 pkt->makeAtomicResponse();
244 return latency;
245}
246void
247X86ISA::Interrupts::requestInterrupt(uint8_t vector,
248 uint8_t deliveryMode, bool level)
249{
250 /*
251 * Fixed and lowest-priority delivery mode interrupts are handled
252 * using the IRR/ISR registers, checking against the TPR, etc.
253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 */
255 if (deliveryMode == DeliveryMode::Fixed ||
256 deliveryMode == DeliveryMode::LowestPriority) {
257 DPRINTF(LocalApic, "Interrupt is an %s.\n",
258 DeliveryMode::names[deliveryMode]);
259 // Queue up the interrupt in the IRR.
260 if (vector > IRRV)
261 IRRV = vector;
262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
264 if (level) {
265 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
266 } else {
267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
268 }
269 }
270 } else if (!DeliveryMode::isReserved(deliveryMode)) {
271 DPRINTF(LocalApic, "Interrupt is an %s.\n",
272 DeliveryMode::names[deliveryMode]);
273 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
274 pendingUnmaskableInt = pendingSmi = true;
275 smiVector = vector;
276 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
277 pendingUnmaskableInt = pendingNmi = true;
278 nmiVector = vector;
279 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
280 pendingExtInt = true;
281 extIntVector = vector;
282 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
283 pendingUnmaskableInt = pendingInit = true;
284 initVector = vector;
285 } else if (deliveryMode == DeliveryMode::SIPI &&
286 !pendingStartup && !startedUp) {
287 pendingUnmaskableInt = pendingStartup = true;
288 startupVector = vector;
289 }
290 }
291 cpu->wakeup();
292}
293
294
295void
296X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
297{
298 cpu = newCPU;
299 assert(cpu);
300 regs[APIC_ID] = (cpu->cpuId() << 24);
301}
302
303
304Tick
305X86ISA::Interrupts::recvMessage(PacketPtr pkt)
306{
307 uint8_t id = (regs[APIC_ID] >> 24);
308 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
309 assert(pkt->cmd == MemCmd::MessageReq);
310 switch(offset)
311 {
312 case 0:
313 {
314 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
315 DPRINTF(LocalApic,
316 "Got Trigger Interrupt message with vector %#x.\n",
317 message.vector);
318 // Make sure we're really supposed to get this.
319 assert((message.destMode == 0 && message.destination == id) ||
320 (bits((int)message.destination, id)));
321
322 requestInterrupt(message.vector,
323 message.deliveryMode, message.trigger);
324 }
325 break;
326 default:
327 panic("Local apic got unknown interrupt message at offset %#x.\n",
328 offset);
329 break;
330 }
331 pkt->makeAtomicResponse();
332 return latency;
333}
334
335
336Tick
337X86ISA::Interrupts::recvResponse(PacketPtr pkt)
338{
339 assert(!pkt->isError());
340 assert(pkt->cmd == MemCmd::MessageResp);
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
64
65int
66divideFromConf(uint32_t conf)
67{
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
72 shift = (shift + 1) % 8;
73 return 1 << shift;
74}
75
76namespace X86ISA
77{
78
79ApicRegIndex
80decodeAddr(Addr paddr)
81{
82 ApicRegIndex regNum;
83 paddr &= ~mask(3);
84 switch (paddr)
85 {
86 case 0x20:
87 regNum = APIC_ID;
88 break;
89 case 0x30:
90 regNum = APIC_VERSION;
91 break;
92 case 0x80:
93 regNum = APIC_TASK_PRIORITY;
94 break;
95 case 0x90:
96 regNum = APIC_ARBITRATION_PRIORITY;
97 break;
98 case 0xA0:
99 regNum = APIC_PROCESSOR_PRIORITY;
100 break;
101 case 0xB0:
102 regNum = APIC_EOI;
103 break;
104 case 0xD0:
105 regNum = APIC_LOGICAL_DESTINATION;
106 break;
107 case 0xE0:
108 regNum = APIC_DESTINATION_FORMAT;
109 break;
110 case 0xF0:
111 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
112 break;
113 case 0x100:
114 case 0x108:
115 case 0x110:
116 case 0x118:
117 case 0x120:
118 case 0x128:
119 case 0x130:
120 case 0x138:
121 case 0x140:
122 case 0x148:
123 case 0x150:
124 case 0x158:
125 case 0x160:
126 case 0x168:
127 case 0x170:
128 case 0x178:
129 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
130 break;
131 case 0x180:
132 case 0x188:
133 case 0x190:
134 case 0x198:
135 case 0x1A0:
136 case 0x1A8:
137 case 0x1B0:
138 case 0x1B8:
139 case 0x1C0:
140 case 0x1C8:
141 case 0x1D0:
142 case 0x1D8:
143 case 0x1E0:
144 case 0x1E8:
145 case 0x1F0:
146 case 0x1F8:
147 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
148 break;
149 case 0x200:
150 case 0x208:
151 case 0x210:
152 case 0x218:
153 case 0x220:
154 case 0x228:
155 case 0x230:
156 case 0x238:
157 case 0x240:
158 case 0x248:
159 case 0x250:
160 case 0x258:
161 case 0x260:
162 case 0x268:
163 case 0x270:
164 case 0x278:
165 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
166 break;
167 case 0x280:
168 regNum = APIC_ERROR_STATUS;
169 break;
170 case 0x300:
171 regNum = APIC_INTERRUPT_COMMAND_LOW;
172 break;
173 case 0x310:
174 regNum = APIC_INTERRUPT_COMMAND_HIGH;
175 break;
176 case 0x320:
177 regNum = APIC_LVT_TIMER;
178 break;
179 case 0x330:
180 regNum = APIC_LVT_THERMAL_SENSOR;
181 break;
182 case 0x340:
183 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
184 break;
185 case 0x350:
186 regNum = APIC_LVT_LINT0;
187 break;
188 case 0x360:
189 regNum = APIC_LVT_LINT1;
190 break;
191 case 0x370:
192 regNum = APIC_LVT_ERROR;
193 break;
194 case 0x380:
195 regNum = APIC_INITIAL_COUNT;
196 break;
197 case 0x390:
198 regNum = APIC_CURRENT_COUNT;
199 break;
200 case 0x3E0:
201 regNum = APIC_DIVIDE_CONFIGURATION;
202 break;
203 default:
204 // A reserved register field.
205 panic("Accessed reserved register field %#x.\n", paddr);
206 break;
207 }
208 return regNum;
209}
210}
211
212Tick
213X86ISA::Interrupts::read(PacketPtr pkt)
214{
215 Addr offset = pkt->getAddr() - pioAddr;
216 //Make sure we're at least only accessing one register.
217 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
218 panic("Accessed more than one register at a time in the APIC!\n");
219 ApicRegIndex reg = decodeAddr(offset);
220 uint32_t val = htog(readReg(reg));
221 DPRINTF(LocalApic,
222 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 reg, offset, val);
224 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
225 pkt->makeAtomicResponse();
226 return latency;
227}
228
229Tick
230X86ISA::Interrupts::write(PacketPtr pkt)
231{
232 Addr offset = pkt->getAddr() - pioAddr;
233 //Make sure we're at least only accessing one register.
234 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
235 panic("Accessed more than one register at a time in the APIC!\n");
236 ApicRegIndex reg = decodeAddr(offset);
237 uint32_t val = regs[reg];
238 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
239 DPRINTF(LocalApic,
240 "Writing Local APIC register %d at offset %#x as %#x.\n",
241 reg, offset, gtoh(val));
242 setReg(reg, gtoh(val));
243 pkt->makeAtomicResponse();
244 return latency;
245}
246void
247X86ISA::Interrupts::requestInterrupt(uint8_t vector,
248 uint8_t deliveryMode, bool level)
249{
250 /*
251 * Fixed and lowest-priority delivery mode interrupts are handled
252 * using the IRR/ISR registers, checking against the TPR, etc.
253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 */
255 if (deliveryMode == DeliveryMode::Fixed ||
256 deliveryMode == DeliveryMode::LowestPriority) {
257 DPRINTF(LocalApic, "Interrupt is an %s.\n",
258 DeliveryMode::names[deliveryMode]);
259 // Queue up the interrupt in the IRR.
260 if (vector > IRRV)
261 IRRV = vector;
262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
264 if (level) {
265 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
266 } else {
267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
268 }
269 }
270 } else if (!DeliveryMode::isReserved(deliveryMode)) {
271 DPRINTF(LocalApic, "Interrupt is an %s.\n",
272 DeliveryMode::names[deliveryMode]);
273 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
274 pendingUnmaskableInt = pendingSmi = true;
275 smiVector = vector;
276 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
277 pendingUnmaskableInt = pendingNmi = true;
278 nmiVector = vector;
279 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
280 pendingExtInt = true;
281 extIntVector = vector;
282 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
283 pendingUnmaskableInt = pendingInit = true;
284 initVector = vector;
285 } else if (deliveryMode == DeliveryMode::SIPI &&
286 !pendingStartup && !startedUp) {
287 pendingUnmaskableInt = pendingStartup = true;
288 startupVector = vector;
289 }
290 }
291 cpu->wakeup();
292}
293
294
295void
296X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
297{
298 cpu = newCPU;
299 assert(cpu);
300 regs[APIC_ID] = (cpu->cpuId() << 24);
301}
302
303
304Tick
305X86ISA::Interrupts::recvMessage(PacketPtr pkt)
306{
307 uint8_t id = (regs[APIC_ID] >> 24);
308 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
309 assert(pkt->cmd == MemCmd::MessageReq);
310 switch(offset)
311 {
312 case 0:
313 {
314 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
315 DPRINTF(LocalApic,
316 "Got Trigger Interrupt message with vector %#x.\n",
317 message.vector);
318 // Make sure we're really supposed to get this.
319 assert((message.destMode == 0 && message.destination == id) ||
320 (bits((int)message.destination, id)));
321
322 requestInterrupt(message.vector,
323 message.deliveryMode, message.trigger);
324 }
325 break;
326 default:
327 panic("Local apic got unknown interrupt message at offset %#x.\n",
328 offset);
329 break;
330 }
331 pkt->makeAtomicResponse();
332 return latency;
333}
334
335
336Tick
337X86ISA::Interrupts::recvResponse(PacketPtr pkt)
338{
339 assert(!pkt->isError());
340 assert(pkt->cmd == MemCmd::MessageResp);
|
341 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
342 // Record that the ICR is now idle.
343 low.deliveryStatus = 0;
344 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
| 341 if (--pendingIPIs == 0) {
342 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
343 // Record that the ICR is now idle.
344 low.deliveryStatus = 0;
345 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
346 }
|
345 delete pkt->req;
346 delete pkt;
347 DPRINTF(LocalApic, "ICR is now idle.\n");
348 return 0;
349}
350
351
352void
353X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
354{
355 uint8_t id = (regs[APIC_ID] >> 24);
356 range_list.clear();
357 Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
358 x86LocalAPICAddress(id, 0) + PageBytes);
359 range_list.push_back(range);
360 pioAddr = range.start;
361}
362
363
364void
365X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
366{
367 uint8_t id = (regs[APIC_ID] >> 24);
368 range_list.clear();
369 range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
370 x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
371}
372
373
374uint32_t
375X86ISA::Interrupts::readReg(ApicRegIndex reg)
376{
377 if (reg >= APIC_TRIGGER_MODE(0) &&
378 reg <= APIC_TRIGGER_MODE(15)) {
379 panic("Local APIC Trigger Mode registers are unimplemented.\n");
380 }
381 switch (reg) {
382 case APIC_ARBITRATION_PRIORITY:
383 panic("Local APIC Arbitration Priority register unimplemented.\n");
384 break;
385 case APIC_PROCESSOR_PRIORITY:
386 panic("Local APIC Processor Priority register unimplemented.\n");
387 break;
388 case APIC_ERROR_STATUS:
389 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
390 break;
391 case APIC_CURRENT_COUNT:
392 {
393 if (apicTimerEvent.scheduled()) {
394 assert(clock);
395 // Compute how many m5 ticks happen per count.
396 uint64_t ticksPerCount = clock *
397 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
398 // Compute how many m5 ticks are left.
399 uint64_t val = apicTimerEvent.when() - curTick;
400 // Turn that into a count.
401 val = (val + ticksPerCount - 1) / ticksPerCount;
402 return val;
403 } else {
404 return 0;
405 }
406 }
407 default:
408 break;
409 }
410 return regs[reg];
411}
412
413void
414X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
415{
416 uint32_t newVal = val;
417 if (reg >= APIC_IN_SERVICE(0) &&
418 reg <= APIC_IN_SERVICE(15)) {
419 panic("Local APIC In-Service registers are unimplemented.\n");
420 }
421 if (reg >= APIC_TRIGGER_MODE(0) &&
422 reg <= APIC_TRIGGER_MODE(15)) {
423 panic("Local APIC Trigger Mode registers are unimplemented.\n");
424 }
425 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
426 reg <= APIC_INTERRUPT_REQUEST(15)) {
427 panic("Local APIC Interrupt Request registers "
428 "are unimplemented.\n");
429 }
430 switch (reg) {
431 case APIC_ID:
432 newVal = val & 0xFF;
433 break;
434 case APIC_VERSION:
435 // The Local APIC Version register is read only.
436 return;
437 case APIC_TASK_PRIORITY:
438 newVal = val & 0xFF;
439 break;
440 case APIC_ARBITRATION_PRIORITY:
441 panic("Local APIC Arbitration Priority register unimplemented.\n");
442 break;
443 case APIC_PROCESSOR_PRIORITY:
444 panic("Local APIC Processor Priority register unimplemented.\n");
445 break;
446 case APIC_EOI:
447 // Remove the interrupt that just completed from the local apic state.
448 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
449 updateISRV();
450 return;
451 case APIC_LOGICAL_DESTINATION:
452 newVal = val & 0xFF000000;
453 break;
454 case APIC_DESTINATION_FORMAT:
455 newVal = val | 0x0FFFFFFF;
456 break;
457 case APIC_SPURIOUS_INTERRUPT_VECTOR:
458 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
459 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
460 if (val & (1 << 9))
461 warn("Focus processor checking not implemented.\n");
462 break;
463 case APIC_ERROR_STATUS:
464 {
465 if (regs[APIC_INTERNAL_STATE] & 0x1) {
466 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
467 newVal = 0;
468 } else {
469 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
470 return;
471 }
472
473 }
474 break;
475 case APIC_INTERRUPT_COMMAND_LOW:
476 {
477 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
478 // Check if we're already sending an IPI.
479 if (low.deliveryStatus) {
480 newVal = low;
481 break;
482 }
483 low = val;
484 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
485 // Record that an IPI is being sent.
486 low.deliveryStatus = 1;
487 TriggerIntMessage message;
488 message.destination = high.destination;
489 message.vector = low.vector;
490 message.deliveryMode = low.deliveryMode;
491 message.destMode = low.destMode;
492 message.level = low.level;
493 message.trigger = low.trigger;
494 bool timing = sys->getMemoryMode() == Enums::timing;
495 // Be careful no updates of the delivery status bit get lost.
496 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
497 switch (low.destShorthand) {
498 case 0:
| 347 delete pkt->req;
348 delete pkt;
349 DPRINTF(LocalApic, "ICR is now idle.\n");
350 return 0;
351}
352
353
354void
355X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
356{
357 uint8_t id = (regs[APIC_ID] >> 24);
358 range_list.clear();
359 Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
360 x86LocalAPICAddress(id, 0) + PageBytes);
361 range_list.push_back(range);
362 pioAddr = range.start;
363}
364
365
366void
367X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
368{
369 uint8_t id = (regs[APIC_ID] >> 24);
370 range_list.clear();
371 range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
372 x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
373}
374
375
376uint32_t
377X86ISA::Interrupts::readReg(ApicRegIndex reg)
378{
379 if (reg >= APIC_TRIGGER_MODE(0) &&
380 reg <= APIC_TRIGGER_MODE(15)) {
381 panic("Local APIC Trigger Mode registers are unimplemented.\n");
382 }
383 switch (reg) {
384 case APIC_ARBITRATION_PRIORITY:
385 panic("Local APIC Arbitration Priority register unimplemented.\n");
386 break;
387 case APIC_PROCESSOR_PRIORITY:
388 panic("Local APIC Processor Priority register unimplemented.\n");
389 break;
390 case APIC_ERROR_STATUS:
391 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
392 break;
393 case APIC_CURRENT_COUNT:
394 {
395 if (apicTimerEvent.scheduled()) {
396 assert(clock);
397 // Compute how many m5 ticks happen per count.
398 uint64_t ticksPerCount = clock *
399 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
400 // Compute how many m5 ticks are left.
401 uint64_t val = apicTimerEvent.when() - curTick;
402 // Turn that into a count.
403 val = (val + ticksPerCount - 1) / ticksPerCount;
404 return val;
405 } else {
406 return 0;
407 }
408 }
409 default:
410 break;
411 }
412 return regs[reg];
413}
414
415void
416X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
417{
418 uint32_t newVal = val;
419 if (reg >= APIC_IN_SERVICE(0) &&
420 reg <= APIC_IN_SERVICE(15)) {
421 panic("Local APIC In-Service registers are unimplemented.\n");
422 }
423 if (reg >= APIC_TRIGGER_MODE(0) &&
424 reg <= APIC_TRIGGER_MODE(15)) {
425 panic("Local APIC Trigger Mode registers are unimplemented.\n");
426 }
427 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
428 reg <= APIC_INTERRUPT_REQUEST(15)) {
429 panic("Local APIC Interrupt Request registers "
430 "are unimplemented.\n");
431 }
432 switch (reg) {
433 case APIC_ID:
434 newVal = val & 0xFF;
435 break;
436 case APIC_VERSION:
437 // The Local APIC Version register is read only.
438 return;
439 case APIC_TASK_PRIORITY:
440 newVal = val & 0xFF;
441 break;
442 case APIC_ARBITRATION_PRIORITY:
443 panic("Local APIC Arbitration Priority register unimplemented.\n");
444 break;
445 case APIC_PROCESSOR_PRIORITY:
446 panic("Local APIC Processor Priority register unimplemented.\n");
447 break;
448 case APIC_EOI:
449 // Remove the interrupt that just completed from the local apic state.
450 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
451 updateISRV();
452 return;
453 case APIC_LOGICAL_DESTINATION:
454 newVal = val & 0xFF000000;
455 break;
456 case APIC_DESTINATION_FORMAT:
457 newVal = val | 0x0FFFFFFF;
458 break;
459 case APIC_SPURIOUS_INTERRUPT_VECTOR:
460 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
461 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
462 if (val & (1 << 9))
463 warn("Focus processor checking not implemented.\n");
464 break;
465 case APIC_ERROR_STATUS:
466 {
467 if (regs[APIC_INTERNAL_STATE] & 0x1) {
468 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
469 newVal = 0;
470 } else {
471 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
472 return;
473 }
474
475 }
476 break;
477 case APIC_INTERRUPT_COMMAND_LOW:
478 {
479 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
480 // Check if we're already sending an IPI.
481 if (low.deliveryStatus) {
482 newVal = low;
483 break;
484 }
485 low = val;
486 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
487 // Record that an IPI is being sent.
488 low.deliveryStatus = 1;
489 TriggerIntMessage message;
490 message.destination = high.destination;
491 message.vector = low.vector;
492 message.deliveryMode = low.deliveryMode;
493 message.destMode = low.destMode;
494 message.level = low.level;
495 message.trigger = low.trigger;
496 bool timing = sys->getMemoryMode() == Enums::timing;
497 // Be careful no updates of the delivery status bit get lost.
498 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
499 switch (low.destShorthand) {
500 case 0:
|
| 501 pendingIPIs++;
|
499 intPort->sendMessage(message, timing);
500 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
501 break;
502 case 1:
| 502 intPort->sendMessage(message, timing);
503 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
504 break;
505 case 1:
|
503 panic("Self IPIs aren't implemented.\n");
| 506 newVal = val;
507 requestInterrupt(message.vector,
508 message.deliveryMode, message.trigger);
|
504 break;
505 case 2:
| 509 break;
510 case 2:
|
506 panic("Broadcast including self IPIs aren't implemented.\n");
507 break;
| 511 requestInterrupt(message.vector,
512 message.deliveryMode, message.trigger);
513 // Fall through
|
508 case 3:
| 514 case 3:
|
509 panic("Broadcast excluding self IPIs aren't implemented.\n");
| 515 {
516 int numContexts = sys->numContexts();
517 pendingIPIs += (numContexts - 1);
518 // We have no way to get at the thread context we're part
519 // of, so we'll just have to go with the CPU for now.
520 hack_once("Broadcast IPIs can't handle more than "
521 "one context per CPU.\n");
522 int myId = cpu->getContext(0)->contextId();
523 for (int i = 0; i < numContexts; i++) {
524 int thisId = sys->getThreadContext(i)->contextId();
525 if (thisId != myId) {
526 PacketPtr pkt = buildIntRequest(thisId, message);
527 if (timing)
528 intPort->sendMessageTiming(pkt, latency);
529 else
530 intPort->sendMessageAtomic(pkt);
531 }
532 }
533 }
534 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
|
510 break;
511 }
512 }
513 break;
514 case APIC_LVT_TIMER:
515 case APIC_LVT_THERMAL_SENSOR:
516 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
517 case APIC_LVT_LINT0:
518 case APIC_LVT_LINT1:
519 case APIC_LVT_ERROR:
520 {
521 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
522 newVal = (val & ~readOnlyMask) |
523 (regs[reg] & readOnlyMask);
524 }
525 break;
526 case APIC_INITIAL_COUNT:
527 {
528 assert(clock);
529 newVal = bits(val, 31, 0);
530 // Compute how many timer ticks we're being programmed for.
531 uint64_t newCount = newVal *
532 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
533 // Schedule on the edge of the next tick plus the new count.
534 Tick offset = curTick % clock;
535 if (offset) {
536 reschedule(apicTimerEvent,
537 curTick + (newCount + 1) * clock - offset, true);
538 } else {
539 reschedule(apicTimerEvent,
540 curTick + newCount * clock, true);
541 }
542 }
543 break;
544 case APIC_CURRENT_COUNT:
545 //Local APIC Current Count register is read only.
546 return;
547 case APIC_DIVIDE_CONFIGURATION:
548 newVal = val & 0xB;
549 break;
550 default:
551 break;
552 }
553 regs[reg] = newVal;
554 return;
555}
556
557
558X86ISA::Interrupts::Interrupts(Params * p) :
559 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
560 apicTimerEvent(this),
561 pendingSmi(false), smiVector(0),
562 pendingNmi(false), nmiVector(0),
563 pendingExtInt(false), extIntVector(0),
564 pendingInit(false), initVector(0),
565 pendingStartup(false), startupVector(0),
| 535 break;
536 }
537 }
538 break;
539 case APIC_LVT_TIMER:
540 case APIC_LVT_THERMAL_SENSOR:
541 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
542 case APIC_LVT_LINT0:
543 case APIC_LVT_LINT1:
544 case APIC_LVT_ERROR:
545 {
546 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
547 newVal = (val & ~readOnlyMask) |
548 (regs[reg] & readOnlyMask);
549 }
550 break;
551 case APIC_INITIAL_COUNT:
552 {
553 assert(clock);
554 newVal = bits(val, 31, 0);
555 // Compute how many timer ticks we're being programmed for.
556 uint64_t newCount = newVal *
557 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
558 // Schedule on the edge of the next tick plus the new count.
559 Tick offset = curTick % clock;
560 if (offset) {
561 reschedule(apicTimerEvent,
562 curTick + (newCount + 1) * clock - offset, true);
563 } else {
564 reschedule(apicTimerEvent,
565 curTick + newCount * clock, true);
566 }
567 }
568 break;
569 case APIC_CURRENT_COUNT:
570 //Local APIC Current Count register is read only.
571 return;
572 case APIC_DIVIDE_CONFIGURATION:
573 newVal = val & 0xB;
574 break;
575 default:
576 break;
577 }
578 regs[reg] = newVal;
579 return;
580}
581
582
583X86ISA::Interrupts::Interrupts(Params * p) :
584 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
585 apicTimerEvent(this),
586 pendingSmi(false), smiVector(0),
587 pendingNmi(false), nmiVector(0),
588 pendingExtInt(false), extIntVector(0),
589 pendingInit(false), initVector(0),
590 pendingStartup(false), startupVector(0),
|
566 startedUp(false), pendingUnmaskableInt(false)
| 591 startedUp(false), pendingUnmaskableInt(false),
592 pendingIPIs(0)
|
567{
568 pioSize = PageBytes;
569 memset(regs, 0, sizeof(regs));
570 //Set the local apic DFR to the flat model.
571 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
572 ISRV = 0;
573 IRRV = 0;
574}
575
576
577bool
578X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
579{
580 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
581 if (pendingUnmaskableInt) {
582 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
583 return true;
584 }
585 if (rflags.intf) {
586 if (pendingExtInt) {
587 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
588 return true;
589 }
590 if (IRRV > ISRV && bits(IRRV, 7, 4) >
591 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
592 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
593 return true;
594 }
595 }
596 return false;
597}
598
599Fault
600X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
601{
602 assert(checkInterrupts(tc));
603 // These are all probably fairly uncommon, so we'll make them easier to
604 // check for.
605 if (pendingUnmaskableInt) {
606 if (pendingSmi) {
607 DPRINTF(LocalApic, "Generated SMI fault object.\n");
608 return new SystemManagementInterrupt();
609 } else if (pendingNmi) {
610 DPRINTF(LocalApic, "Generated NMI fault object.\n");
611 return new NonMaskableInterrupt(nmiVector);
612 } else if (pendingInit) {
613 DPRINTF(LocalApic, "Generated INIT fault object.\n");
614 return new InitInterrupt(initVector);
615 } else if (pendingStartup) {
616 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
617 return new StartupInterrupt(startupVector);
618 } else {
619 panic("pendingUnmaskableInt set, but no unmaskable "
620 "ints were pending.\n");
621 return NoFault;
622 }
623 } else if (pendingExtInt) {
624 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
625 return new ExternalInterrupt(extIntVector);
626 } else {
627 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
628 // The only thing left are fixed and lowest priority interrupts.
629 return new ExternalInterrupt(IRRV);
630 }
631}
632
633void
634X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
635{
636 assert(checkInterrupts(tc));
637 if (pendingUnmaskableInt) {
638 if (pendingSmi) {
639 DPRINTF(LocalApic, "SMI sent to core.\n");
640 pendingSmi = false;
641 } else if (pendingNmi) {
642 DPRINTF(LocalApic, "NMI sent to core.\n");
643 pendingNmi = false;
644 } else if (pendingInit) {
645 DPRINTF(LocalApic, "Init sent to core.\n");
646 pendingInit = false;
647 startedUp = false;
648 } else if (pendingStartup) {
649 DPRINTF(LocalApic, "SIPI sent to core.\n");
650 pendingStartup = false;
651 startedUp = true;
652 }
653 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
654 pendingUnmaskableInt = false;
655 } else if (pendingExtInt) {
656 pendingExtInt = false;
657 } else {
658 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
659 // Mark the interrupt as "in service".
660 ISRV = IRRV;
661 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
662 // Clear it out of the IRR.
663 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
664 updateIRRV();
665 }
666}
667
668X86ISA::Interrupts *
669X86LocalApicParams::create()
670{
671 return new X86ISA::Interrupts(this);
672}
| 593{
594 pioSize = PageBytes;
595 memset(regs, 0, sizeof(regs));
596 //Set the local apic DFR to the flat model.
597 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
598 ISRV = 0;
599 IRRV = 0;
600}
601
602
603bool
604X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
605{
606 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
607 if (pendingUnmaskableInt) {
608 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
609 return true;
610 }
611 if (rflags.intf) {
612 if (pendingExtInt) {
613 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
614 return true;
615 }
616 if (IRRV > ISRV && bits(IRRV, 7, 4) >
617 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
618 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
619 return true;
620 }
621 }
622 return false;
623}
624
625Fault
626X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
627{
628 assert(checkInterrupts(tc));
629 // These are all probably fairly uncommon, so we'll make them easier to
630 // check for.
631 if (pendingUnmaskableInt) {
632 if (pendingSmi) {
633 DPRINTF(LocalApic, "Generated SMI fault object.\n");
634 return new SystemManagementInterrupt();
635 } else if (pendingNmi) {
636 DPRINTF(LocalApic, "Generated NMI fault object.\n");
637 return new NonMaskableInterrupt(nmiVector);
638 } else if (pendingInit) {
639 DPRINTF(LocalApic, "Generated INIT fault object.\n");
640 return new InitInterrupt(initVector);
641 } else if (pendingStartup) {
642 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
643 return new StartupInterrupt(startupVector);
644 } else {
645 panic("pendingUnmaskableInt set, but no unmaskable "
646 "ints were pending.\n");
647 return NoFault;
648 }
649 } else if (pendingExtInt) {
650 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
651 return new ExternalInterrupt(extIntVector);
652 } else {
653 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
654 // The only thing left are fixed and lowest priority interrupts.
655 return new ExternalInterrupt(IRRV);
656 }
657}
658
659void
660X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
661{
662 assert(checkInterrupts(tc));
663 if (pendingUnmaskableInt) {
664 if (pendingSmi) {
665 DPRINTF(LocalApic, "SMI sent to core.\n");
666 pendingSmi = false;
667 } else if (pendingNmi) {
668 DPRINTF(LocalApic, "NMI sent to core.\n");
669 pendingNmi = false;
670 } else if (pendingInit) {
671 DPRINTF(LocalApic, "Init sent to core.\n");
672 pendingInit = false;
673 startedUp = false;
674 } else if (pendingStartup) {
675 DPRINTF(LocalApic, "SIPI sent to core.\n");
676 pendingStartup = false;
677 startedUp = true;
678 }
679 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
680 pendingUnmaskableInt = false;
681 } else if (pendingExtInt) {
682 pendingExtInt = false;
683 } else {
684 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
685 // Mark the interrupt as "in service".
686 ISRV = IRRV;
687 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
688 // Clear it out of the IRR.
689 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
690 updateIRRV();
691 }
692}
693
694X86ISA::Interrupts *
695X86LocalApicParams::create()
696{
697 return new X86ISA::Interrupts(this);
698}
|