1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
64
65int
66divideFromConf(uint32_t conf)
67{
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
72 shift = (shift + 1) % 8;
73 return 1 << shift;
74}
75
76namespace X86ISA
77{
78
79ApicRegIndex
80decodeAddr(Addr paddr)
81{
82 ApicRegIndex regNum;
83 paddr &= ~mask(3);
84 switch (paddr)
85 {
86 case 0x20:
87 regNum = APIC_ID;
88 break;
89 case 0x30:
90 regNum = APIC_VERSION;
91 break;
92 case 0x80:
93 regNum = APIC_TASK_PRIORITY;
94 break;
95 case 0x90:
96 regNum = APIC_ARBITRATION_PRIORITY;
97 break;
98 case 0xA0:
99 regNum = APIC_PROCESSOR_PRIORITY;
100 break;
101 case 0xB0:
102 regNum = APIC_EOI;
103 break;
104 case 0xD0:
105 regNum = APIC_LOGICAL_DESTINATION;
106 break;
107 case 0xE0:
108 regNum = APIC_DESTINATION_FORMAT;
109 break;
110 case 0xF0:
111 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
112 break;
113 case 0x100:
114 case 0x108:
115 case 0x110:
116 case 0x118:
117 case 0x120:
118 case 0x128:
119 case 0x130:
120 case 0x138:
121 case 0x140:
122 case 0x148:
123 case 0x150:
124 case 0x158:
125 case 0x160:
126 case 0x168:
127 case 0x170:
128 case 0x178:
129 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
130 break;
131 case 0x180:
132 case 0x188:
133 case 0x190:
134 case 0x198:
135 case 0x1A0:
136 case 0x1A8:
137 case 0x1B0:
138 case 0x1B8:
139 case 0x1C0:
140 case 0x1C8:
141 case 0x1D0:
142 case 0x1D8:
143 case 0x1E0:
144 case 0x1E8:
145 case 0x1F0:
146 case 0x1F8:
147 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
148 break;
149 case 0x200:
150 case 0x208:
151 case 0x210:
152 case 0x218:
153 case 0x220:
154 case 0x228:
155 case 0x230:
156 case 0x238:
157 case 0x240:
158 case 0x248:
159 case 0x250:
160 case 0x258:
161 case 0x260:
162 case 0x268:
163 case 0x270:
164 case 0x278:
165 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
166 break;
167 case 0x280:
168 regNum = APIC_ERROR_STATUS;
169 break;
170 case 0x300:
171 regNum = APIC_INTERRUPT_COMMAND_LOW;
172 break;
173 case 0x310:
174 regNum = APIC_INTERRUPT_COMMAND_HIGH;
175 break;
176 case 0x320:
177 regNum = APIC_LVT_TIMER;
178 break;
179 case 0x330:
180 regNum = APIC_LVT_THERMAL_SENSOR;
181 break;
182 case 0x340:
183 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
184 break;
185 case 0x350:
186 regNum = APIC_LVT_LINT0;
187 break;
188 case 0x360:
189 regNum = APIC_LVT_LINT1;
190 break;
191 case 0x370:
192 regNum = APIC_LVT_ERROR;
193 break;
194 case 0x380:
195 regNum = APIC_INITIAL_COUNT;
196 break;
197 case 0x390:
198 regNum = APIC_CURRENT_COUNT;
199 break;
200 case 0x3E0:
201 regNum = APIC_DIVIDE_CONFIGURATION;
202 break;
203 default:
204 // A reserved register field.
205 panic("Accessed reserved register field %#x.\n", paddr);
206 break;
207 }
208 return regNum;
209}
210}
211
212Tick
213X86ISA::Interrupts::read(PacketPtr pkt)
214{
215 Addr offset = pkt->getAddr() - pioAddr;
216 //Make sure we're at least only accessing one register.
217 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
218 panic("Accessed more than one register at a time in the APIC!\n");
219 ApicRegIndex reg = decodeAddr(offset);
220 uint32_t val = htog(readReg(reg));
221 DPRINTF(LocalApic,
222 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 reg, offset, val);
224 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
225 pkt->makeAtomicResponse();
226 return latency;
227}
228
229Tick
230X86ISA::Interrupts::write(PacketPtr pkt)
231{
232 Addr offset = pkt->getAddr() - pioAddr;
233 //Make sure we're at least only accessing one register.
234 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
235 panic("Accessed more than one register at a time in the APIC!\n");
236 ApicRegIndex reg = decodeAddr(offset);
237 uint32_t val = regs[reg];
238 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
239 DPRINTF(LocalApic,
240 "Writing Local APIC register %d at offset %#x as %#x.\n",
241 reg, offset, gtoh(val));
242 setReg(reg, gtoh(val));
243 pkt->makeAtomicResponse();
244 return latency;
245}
246void
247X86ISA::Interrupts::requestInterrupt(uint8_t vector,
248 uint8_t deliveryMode, bool level)
249{
250 /*
251 * Fixed and lowest-priority delivery mode interrupts are handled
252 * using the IRR/ISR registers, checking against the TPR, etc.
253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 */
255 if (deliveryMode == DeliveryMode::Fixed ||
256 deliveryMode == DeliveryMode::LowestPriority) {
257 DPRINTF(LocalApic, "Interrupt is an %s.\n",
258 DeliveryMode::names[deliveryMode]);
259 // Queue up the interrupt in the IRR.
260 if (vector > IRRV)
261 IRRV = vector;
262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
264 if (level) {
265 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
266 } else {
267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
268 }
269 }
270 } else if (!DeliveryMode::isReserved(deliveryMode)) {
271 DPRINTF(LocalApic, "Interrupt is an %s.\n",
272 DeliveryMode::names[deliveryMode]);
273 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
274 pendingUnmaskableInt = pendingSmi = true;
275 smiVector = vector;
276 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
277 pendingUnmaskableInt = pendingNmi = true;
278 nmiVector = vector;
279 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
280 pendingExtInt = true;
281 extIntVector = vector;
282 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
283 pendingUnmaskableInt = pendingInit = true;
284 initVector = vector;
285 } else if (deliveryMode == DeliveryMode::SIPI && !pendingStartup) {
286 pendingUnmaskableInt = pendingStartup = true;
287 startupVector = vector;
288 }
289 }
290 cpu->wakeup();
291}
292
293
294void
295X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
296{
297 cpu = newCPU;
298 assert(cpu);
299 regs[APIC_ID] = (cpu->cpuId() << 24);
300}
301
302
303Tick
304X86ISA::Interrupts::recvMessage(PacketPtr pkt)
305{
306 uint8_t id = (regs[APIC_ID] >> 24);
307 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
308 assert(pkt->cmd == MemCmd::MessageReq);
309 switch(offset)
310 {
311 case 0:
312 {
313 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
314 DPRINTF(LocalApic,
315 "Got Trigger Interrupt message with vector %#x.\n",
316 message.vector);
317 // Make sure we're really supposed to get this.
318 assert((message.destMode == 0 && message.destination == id) ||
319 (bits((int)message.destination, id)));
320
321 requestInterrupt(message.vector,
322 message.deliveryMode, message.trigger);
323 }
324 break;
325 default:
326 panic("Local apic got unknown interrupt message at offset %#x.\n",
327 offset);
328 break;
329 }
330 pkt->makeAtomicResponse();
331 return latency;
332}
333
334
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
64
65int
66divideFromConf(uint32_t conf)
67{
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
72 shift = (shift + 1) % 8;
73 return 1 << shift;
74}
75
76namespace X86ISA
77{
78
79ApicRegIndex
80decodeAddr(Addr paddr)
81{
82 ApicRegIndex regNum;
83 paddr &= ~mask(3);
84 switch (paddr)
85 {
86 case 0x20:
87 regNum = APIC_ID;
88 break;
89 case 0x30:
90 regNum = APIC_VERSION;
91 break;
92 case 0x80:
93 regNum = APIC_TASK_PRIORITY;
94 break;
95 case 0x90:
96 regNum = APIC_ARBITRATION_PRIORITY;
97 break;
98 case 0xA0:
99 regNum = APIC_PROCESSOR_PRIORITY;
100 break;
101 case 0xB0:
102 regNum = APIC_EOI;
103 break;
104 case 0xD0:
105 regNum = APIC_LOGICAL_DESTINATION;
106 break;
107 case 0xE0:
108 regNum = APIC_DESTINATION_FORMAT;
109 break;
110 case 0xF0:
111 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
112 break;
113 case 0x100:
114 case 0x108:
115 case 0x110:
116 case 0x118:
117 case 0x120:
118 case 0x128:
119 case 0x130:
120 case 0x138:
121 case 0x140:
122 case 0x148:
123 case 0x150:
124 case 0x158:
125 case 0x160:
126 case 0x168:
127 case 0x170:
128 case 0x178:
129 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
130 break;
131 case 0x180:
132 case 0x188:
133 case 0x190:
134 case 0x198:
135 case 0x1A0:
136 case 0x1A8:
137 case 0x1B0:
138 case 0x1B8:
139 case 0x1C0:
140 case 0x1C8:
141 case 0x1D0:
142 case 0x1D8:
143 case 0x1E0:
144 case 0x1E8:
145 case 0x1F0:
146 case 0x1F8:
147 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
148 break;
149 case 0x200:
150 case 0x208:
151 case 0x210:
152 case 0x218:
153 case 0x220:
154 case 0x228:
155 case 0x230:
156 case 0x238:
157 case 0x240:
158 case 0x248:
159 case 0x250:
160 case 0x258:
161 case 0x260:
162 case 0x268:
163 case 0x270:
164 case 0x278:
165 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
166 break;
167 case 0x280:
168 regNum = APIC_ERROR_STATUS;
169 break;
170 case 0x300:
171 regNum = APIC_INTERRUPT_COMMAND_LOW;
172 break;
173 case 0x310:
174 regNum = APIC_INTERRUPT_COMMAND_HIGH;
175 break;
176 case 0x320:
177 regNum = APIC_LVT_TIMER;
178 break;
179 case 0x330:
180 regNum = APIC_LVT_THERMAL_SENSOR;
181 break;
182 case 0x340:
183 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
184 break;
185 case 0x350:
186 regNum = APIC_LVT_LINT0;
187 break;
188 case 0x360:
189 regNum = APIC_LVT_LINT1;
190 break;
191 case 0x370:
192 regNum = APIC_LVT_ERROR;
193 break;
194 case 0x380:
195 regNum = APIC_INITIAL_COUNT;
196 break;
197 case 0x390:
198 regNum = APIC_CURRENT_COUNT;
199 break;
200 case 0x3E0:
201 regNum = APIC_DIVIDE_CONFIGURATION;
202 break;
203 default:
204 // A reserved register field.
205 panic("Accessed reserved register field %#x.\n", paddr);
206 break;
207 }
208 return regNum;
209}
210}
211
212Tick
213X86ISA::Interrupts::read(PacketPtr pkt)
214{
215 Addr offset = pkt->getAddr() - pioAddr;
216 //Make sure we're at least only accessing one register.
217 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
218 panic("Accessed more than one register at a time in the APIC!\n");
219 ApicRegIndex reg = decodeAddr(offset);
220 uint32_t val = htog(readReg(reg));
221 DPRINTF(LocalApic,
222 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 reg, offset, val);
224 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
225 pkt->makeAtomicResponse();
226 return latency;
227}
228
229Tick
230X86ISA::Interrupts::write(PacketPtr pkt)
231{
232 Addr offset = pkt->getAddr() - pioAddr;
233 //Make sure we're at least only accessing one register.
234 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
235 panic("Accessed more than one register at a time in the APIC!\n");
236 ApicRegIndex reg = decodeAddr(offset);
237 uint32_t val = regs[reg];
238 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
239 DPRINTF(LocalApic,
240 "Writing Local APIC register %d at offset %#x as %#x.\n",
241 reg, offset, gtoh(val));
242 setReg(reg, gtoh(val));
243 pkt->makeAtomicResponse();
244 return latency;
245}
246void
247X86ISA::Interrupts::requestInterrupt(uint8_t vector,
248 uint8_t deliveryMode, bool level)
249{
250 /*
251 * Fixed and lowest-priority delivery mode interrupts are handled
252 * using the IRR/ISR registers, checking against the TPR, etc.
253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 */
255 if (deliveryMode == DeliveryMode::Fixed ||
256 deliveryMode == DeliveryMode::LowestPriority) {
257 DPRINTF(LocalApic, "Interrupt is an %s.\n",
258 DeliveryMode::names[deliveryMode]);
259 // Queue up the interrupt in the IRR.
260 if (vector > IRRV)
261 IRRV = vector;
262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
264 if (level) {
265 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
266 } else {
267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
268 }
269 }
270 } else if (!DeliveryMode::isReserved(deliveryMode)) {
271 DPRINTF(LocalApic, "Interrupt is an %s.\n",
272 DeliveryMode::names[deliveryMode]);
273 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
274 pendingUnmaskableInt = pendingSmi = true;
275 smiVector = vector;
276 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
277 pendingUnmaskableInt = pendingNmi = true;
278 nmiVector = vector;
279 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
280 pendingExtInt = true;
281 extIntVector = vector;
282 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
283 pendingUnmaskableInt = pendingInit = true;
284 initVector = vector;
285 } else if (deliveryMode == DeliveryMode::SIPI && !pendingStartup) {
286 pendingUnmaskableInt = pendingStartup = true;
287 startupVector = vector;
288 }
289 }
290 cpu->wakeup();
291}
292
293
294void
295X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
296{
297 cpu = newCPU;
298 assert(cpu);
299 regs[APIC_ID] = (cpu->cpuId() << 24);
300}
301
302
303Tick
304X86ISA::Interrupts::recvMessage(PacketPtr pkt)
305{
306 uint8_t id = (regs[APIC_ID] >> 24);
307 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
308 assert(pkt->cmd == MemCmd::MessageReq);
309 switch(offset)
310 {
311 case 0:
312 {
313 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
314 DPRINTF(LocalApic,
315 "Got Trigger Interrupt message with vector %#x.\n",
316 message.vector);
317 // Make sure we're really supposed to get this.
318 assert((message.destMode == 0 && message.destination == id) ||
319 (bits((int)message.destination, id)));
320
321 requestInterrupt(message.vector,
322 message.deliveryMode, message.trigger);
323 }
324 break;
325 default:
326 panic("Local apic got unknown interrupt message at offset %#x.\n",
327 offset);
328 break;
329 }
330 pkt->makeAtomicResponse();
331 return latency;
332}
333
334
|
| 335Tick
336X86ISA::Interrupts::recvResponse(PacketPtr pkt)
337{
338 assert(!pkt->isError());
339 assert(pkt->cmd == MemCmd::MessageResp);
340 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
341 // Record that the ICR is now idle.
342 low.deliveryStatus = 0;
343 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
344 delete pkt->req;
345 delete pkt;
346 DPRINTF(LocalApic, "ICR is now idle.\n");
347 return 0;
348}
349
350
|
335void
336X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
337{
338 uint8_t id = (regs[APIC_ID] >> 24);
339 range_list.clear();
340 Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
341 x86LocalAPICAddress(id, 0) + PageBytes);
342 range_list.push_back(range);
343 pioAddr = range.start;
344}
345
346
347void
348X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
349{
350 uint8_t id = (regs[APIC_ID] >> 24);
351 range_list.clear();
352 range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
353 x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
354}
355
356
357uint32_t
358X86ISA::Interrupts::readReg(ApicRegIndex reg)
359{
360 if (reg >= APIC_TRIGGER_MODE(0) &&
361 reg <= APIC_TRIGGER_MODE(15)) {
362 panic("Local APIC Trigger Mode registers are unimplemented.\n");
363 }
364 switch (reg) {
365 case APIC_ARBITRATION_PRIORITY:
366 panic("Local APIC Arbitration Priority register unimplemented.\n");
367 break;
368 case APIC_PROCESSOR_PRIORITY:
369 panic("Local APIC Processor Priority register unimplemented.\n");
370 break;
371 case APIC_ERROR_STATUS:
372 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
373 break;
374 case APIC_CURRENT_COUNT:
375 {
376 if (apicTimerEvent.scheduled()) {
377 assert(clock);
378 // Compute how many m5 ticks happen per count.
379 uint64_t ticksPerCount = clock *
380 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
381 // Compute how many m5 ticks are left.
382 uint64_t val = apicTimerEvent.when() - curTick;
383 // Turn that into a count.
384 val = (val + ticksPerCount - 1) / ticksPerCount;
385 return val;
386 } else {
387 return 0;
388 }
389 }
390 default:
391 break;
392 }
393 return regs[reg];
394}
395
396void
397X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
398{
399 uint32_t newVal = val;
400 if (reg >= APIC_IN_SERVICE(0) &&
401 reg <= APIC_IN_SERVICE(15)) {
402 panic("Local APIC In-Service registers are unimplemented.\n");
403 }
404 if (reg >= APIC_TRIGGER_MODE(0) &&
405 reg <= APIC_TRIGGER_MODE(15)) {
406 panic("Local APIC Trigger Mode registers are unimplemented.\n");
407 }
408 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
409 reg <= APIC_INTERRUPT_REQUEST(15)) {
410 panic("Local APIC Interrupt Request registers "
411 "are unimplemented.\n");
412 }
413 switch (reg) {
414 case APIC_ID:
415 newVal = val & 0xFF;
416 break;
417 case APIC_VERSION:
418 // The Local APIC Version register is read only.
419 return;
420 case APIC_TASK_PRIORITY:
421 newVal = val & 0xFF;
422 break;
423 case APIC_ARBITRATION_PRIORITY:
424 panic("Local APIC Arbitration Priority register unimplemented.\n");
425 break;
426 case APIC_PROCESSOR_PRIORITY:
427 panic("Local APIC Processor Priority register unimplemented.\n");
428 break;
429 case APIC_EOI:
430 // Remove the interrupt that just completed from the local apic state.
431 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
432 updateISRV();
433 return;
434 case APIC_LOGICAL_DESTINATION:
435 newVal = val & 0xFF000000;
436 break;
437 case APIC_DESTINATION_FORMAT:
438 newVal = val | 0x0FFFFFFF;
439 break;
440 case APIC_SPURIOUS_INTERRUPT_VECTOR:
441 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
442 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
443 if (val & (1 << 9))
444 warn("Focus processor checking not implemented.\n");
445 break;
446 case APIC_ERROR_STATUS:
447 {
448 if (regs[APIC_INTERNAL_STATE] & 0x1) {
449 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
450 newVal = 0;
451 } else {
452 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
453 return;
454 }
455
456 }
457 break;
458 case APIC_INTERRUPT_COMMAND_LOW:
459 {
460 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
461 // Check if we're already sending an IPI.
462 if (low.deliveryStatus) {
463 newVal = low;
464 break;
465 }
466 low = val;
467 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
468 // Record that an IPI is being sent.
469 low.deliveryStatus = 1;
470 TriggerIntMessage message;
471 message.destination = high.destination;
472 message.vector = low.vector;
473 message.deliveryMode = low.deliveryMode;
474 message.destMode = low.destMode;
475 message.level = low.level;
476 message.trigger = low.trigger;
477 bool timing = sys->getMemoryMode() == Enums::timing;
| 351void
352X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
353{
354 uint8_t id = (regs[APIC_ID] >> 24);
355 range_list.clear();
356 Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
357 x86LocalAPICAddress(id, 0) + PageBytes);
358 range_list.push_back(range);
359 pioAddr = range.start;
360}
361
362
363void
364X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
365{
366 uint8_t id = (regs[APIC_ID] >> 24);
367 range_list.clear();
368 range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
369 x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
370}
371
372
373uint32_t
374X86ISA::Interrupts::readReg(ApicRegIndex reg)
375{
376 if (reg >= APIC_TRIGGER_MODE(0) &&
377 reg <= APIC_TRIGGER_MODE(15)) {
378 panic("Local APIC Trigger Mode registers are unimplemented.\n");
379 }
380 switch (reg) {
381 case APIC_ARBITRATION_PRIORITY:
382 panic("Local APIC Arbitration Priority register unimplemented.\n");
383 break;
384 case APIC_PROCESSOR_PRIORITY:
385 panic("Local APIC Processor Priority register unimplemented.\n");
386 break;
387 case APIC_ERROR_STATUS:
388 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
389 break;
390 case APIC_CURRENT_COUNT:
391 {
392 if (apicTimerEvent.scheduled()) {
393 assert(clock);
394 // Compute how many m5 ticks happen per count.
395 uint64_t ticksPerCount = clock *
396 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
397 // Compute how many m5 ticks are left.
398 uint64_t val = apicTimerEvent.when() - curTick;
399 // Turn that into a count.
400 val = (val + ticksPerCount - 1) / ticksPerCount;
401 return val;
402 } else {
403 return 0;
404 }
405 }
406 default:
407 break;
408 }
409 return regs[reg];
410}
411
412void
413X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
414{
415 uint32_t newVal = val;
416 if (reg >= APIC_IN_SERVICE(0) &&
417 reg <= APIC_IN_SERVICE(15)) {
418 panic("Local APIC In-Service registers are unimplemented.\n");
419 }
420 if (reg >= APIC_TRIGGER_MODE(0) &&
421 reg <= APIC_TRIGGER_MODE(15)) {
422 panic("Local APIC Trigger Mode registers are unimplemented.\n");
423 }
424 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
425 reg <= APIC_INTERRUPT_REQUEST(15)) {
426 panic("Local APIC Interrupt Request registers "
427 "are unimplemented.\n");
428 }
429 switch (reg) {
430 case APIC_ID:
431 newVal = val & 0xFF;
432 break;
433 case APIC_VERSION:
434 // The Local APIC Version register is read only.
435 return;
436 case APIC_TASK_PRIORITY:
437 newVal = val & 0xFF;
438 break;
439 case APIC_ARBITRATION_PRIORITY:
440 panic("Local APIC Arbitration Priority register unimplemented.\n");
441 break;
442 case APIC_PROCESSOR_PRIORITY:
443 panic("Local APIC Processor Priority register unimplemented.\n");
444 break;
445 case APIC_EOI:
446 // Remove the interrupt that just completed from the local apic state.
447 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
448 updateISRV();
449 return;
450 case APIC_LOGICAL_DESTINATION:
451 newVal = val & 0xFF000000;
452 break;
453 case APIC_DESTINATION_FORMAT:
454 newVal = val | 0x0FFFFFFF;
455 break;
456 case APIC_SPURIOUS_INTERRUPT_VECTOR:
457 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
458 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
459 if (val & (1 << 9))
460 warn("Focus processor checking not implemented.\n");
461 break;
462 case APIC_ERROR_STATUS:
463 {
464 if (regs[APIC_INTERNAL_STATE] & 0x1) {
465 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
466 newVal = 0;
467 } else {
468 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
469 return;
470 }
471
472 }
473 break;
474 case APIC_INTERRUPT_COMMAND_LOW:
475 {
476 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
477 // Check if we're already sending an IPI.
478 if (low.deliveryStatus) {
479 newVal = low;
480 break;
481 }
482 low = val;
483 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
484 // Record that an IPI is being sent.
485 low.deliveryStatus = 1;
486 TriggerIntMessage message;
487 message.destination = high.destination;
488 message.vector = low.vector;
489 message.deliveryMode = low.deliveryMode;
490 message.destMode = low.destMode;
491 message.level = low.level;
492 message.trigger = low.trigger;
493 bool timing = sys->getMemoryMode() == Enums::timing;
|
| 494 // Be careful no updates of the delivery status bit get lost.
495 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
|
478 switch (low.destShorthand) {
479 case 0:
480 intPort->sendMessage(message, timing);
| 496 switch (low.destShorthand) {
497 case 0:
498 intPort->sendMessage(message, timing);
|
| 499 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
|
481 break;
482 case 1:
483 panic("Self IPIs aren't implemented.\n");
484 break;
485 case 2:
486 panic("Broadcast including self IPIs aren't implemented.\n");
487 break;
488 case 3:
489 panic("Broadcast excluding self IPIs aren't implemented.\n");
490 break;
491 }
492 }
493 break;
494 case APIC_LVT_TIMER:
495 case APIC_LVT_THERMAL_SENSOR:
496 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
497 case APIC_LVT_LINT0:
498 case APIC_LVT_LINT1:
499 case APIC_LVT_ERROR:
500 {
501 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
502 newVal = (val & ~readOnlyMask) |
503 (regs[reg] & readOnlyMask);
504 }
505 break;
506 case APIC_INITIAL_COUNT:
507 {
508 assert(clock);
509 newVal = bits(val, 31, 0);
510 // Compute how many timer ticks we're being programmed for.
511 uint64_t newCount = newVal *
512 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
513 // Schedule on the edge of the next tick plus the new count.
514 Tick offset = curTick % clock;
515 if (offset) {
516 reschedule(apicTimerEvent,
517 curTick + (newCount + 1) * clock - offset, true);
518 } else {
519 reschedule(apicTimerEvent,
520 curTick + newCount * clock, true);
521 }
522 }
523 break;
524 case APIC_CURRENT_COUNT:
525 //Local APIC Current Count register is read only.
526 return;
527 case APIC_DIVIDE_CONFIGURATION:
528 newVal = val & 0xB;
529 break;
530 default:
531 break;
532 }
533 regs[reg] = newVal;
534 return;
535}
536
537
538X86ISA::Interrupts::Interrupts(Params * p) :
539 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
540 apicTimerEvent(this),
541 pendingSmi(false), smiVector(0),
542 pendingNmi(false), nmiVector(0),
543 pendingExtInt(false), extIntVector(0),
544 pendingInit(false), initVector(0),
545 pendingStartup(false), startupVector(0),
546 pendingUnmaskableInt(false)
547{
548 pioSize = PageBytes;
549 memset(regs, 0, sizeof(regs));
550 //Set the local apic DFR to the flat model.
551 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
552 ISRV = 0;
553 IRRV = 0;
554}
555
556
557bool
558X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
559{
560 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
561 if (pendingUnmaskableInt) {
562 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
563 return true;
564 }
565 if (rflags.intf) {
566 if (pendingExtInt) {
567 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
568 return true;
569 }
570 if (IRRV > ISRV && bits(IRRV, 7, 4) >
571 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
572 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
573 return true;
574 }
575 }
576 return false;
577}
578
579Fault
580X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
581{
582 assert(checkInterrupts(tc));
583 // These are all probably fairly uncommon, so we'll make them easier to
584 // check for.
585 if (pendingUnmaskableInt) {
586 if (pendingSmi) {
587 DPRINTF(LocalApic, "Generated SMI fault object.\n");
588 return new SystemManagementInterrupt();
589 } else if (pendingNmi) {
590 DPRINTF(LocalApic, "Generated NMI fault object.\n");
591 return new NonMaskableInterrupt(nmiVector);
592 } else if (pendingInit) {
593 DPRINTF(LocalApic, "Generated INIT fault object.\n");
594 return new InitInterrupt(initVector);
595 } else if (pendingStartup) {
596 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
597 return new StartupInterrupt(startupVector);
598 } else {
599 panic("pendingUnmaskableInt set, but no unmaskable "
600 "ints were pending.\n");
601 return NoFault;
602 }
603 } else if (pendingExtInt) {
604 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
605 return new ExternalInterrupt(extIntVector);
606 } else {
607 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
608 // The only thing left are fixed and lowest priority interrupts.
609 return new ExternalInterrupt(IRRV);
610 }
611}
612
613void
614X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
615{
616 assert(checkInterrupts(tc));
617 if (pendingUnmaskableInt) {
618 if (pendingSmi) {
619 DPRINTF(LocalApic, "SMI sent to core.\n");
620 pendingSmi = false;
621 } else if (pendingNmi) {
622 DPRINTF(LocalApic, "NMI sent to core.\n");
623 pendingNmi = false;
624 } else if (pendingInit) {
625 DPRINTF(LocalApic, "Init sent to core.\n");
626 pendingInit = false;
627 } else if (pendingStartup) {
628 DPRINTF(LocalApic, "SIPI sent to core.\n");
629 pendingStartup = false;
630 }
631 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
632 pendingUnmaskableInt = false;
633 } else if (pendingExtInt) {
634 pendingExtInt = false;
635 } else {
636 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
637 // Mark the interrupt as "in service".
638 ISRV = IRRV;
639 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
640 // Clear it out of the IRR.
641 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
642 updateIRRV();
643 }
644}
645
646X86ISA::Interrupts *
647X86LocalApicParams::create()
648{
649 return new X86ISA::Interrupts(this);
650}
| 500 break;
501 case 1:
502 panic("Self IPIs aren't implemented.\n");
503 break;
504 case 2:
505 panic("Broadcast including self IPIs aren't implemented.\n");
506 break;
507 case 3:
508 panic("Broadcast excluding self IPIs aren't implemented.\n");
509 break;
510 }
511 }
512 break;
513 case APIC_LVT_TIMER:
514 case APIC_LVT_THERMAL_SENSOR:
515 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
516 case APIC_LVT_LINT0:
517 case APIC_LVT_LINT1:
518 case APIC_LVT_ERROR:
519 {
520 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
521 newVal = (val & ~readOnlyMask) |
522 (regs[reg] & readOnlyMask);
523 }
524 break;
525 case APIC_INITIAL_COUNT:
526 {
527 assert(clock);
528 newVal = bits(val, 31, 0);
529 // Compute how many timer ticks we're being programmed for.
530 uint64_t newCount = newVal *
531 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
532 // Schedule on the edge of the next tick plus the new count.
533 Tick offset = curTick % clock;
534 if (offset) {
535 reschedule(apicTimerEvent,
536 curTick + (newCount + 1) * clock - offset, true);
537 } else {
538 reschedule(apicTimerEvent,
539 curTick + newCount * clock, true);
540 }
541 }
542 break;
543 case APIC_CURRENT_COUNT:
544 //Local APIC Current Count register is read only.
545 return;
546 case APIC_DIVIDE_CONFIGURATION:
547 newVal = val & 0xB;
548 break;
549 default:
550 break;
551 }
552 regs[reg] = newVal;
553 return;
554}
555
556
557X86ISA::Interrupts::Interrupts(Params * p) :
558 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
559 apicTimerEvent(this),
560 pendingSmi(false), smiVector(0),
561 pendingNmi(false), nmiVector(0),
562 pendingExtInt(false), extIntVector(0),
563 pendingInit(false), initVector(0),
564 pendingStartup(false), startupVector(0),
565 pendingUnmaskableInt(false)
566{
567 pioSize = PageBytes;
568 memset(regs, 0, sizeof(regs));
569 //Set the local apic DFR to the flat model.
570 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
571 ISRV = 0;
572 IRRV = 0;
573}
574
575
576bool
577X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
578{
579 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
580 if (pendingUnmaskableInt) {
581 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
582 return true;
583 }
584 if (rflags.intf) {
585 if (pendingExtInt) {
586 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
587 return true;
588 }
589 if (IRRV > ISRV && bits(IRRV, 7, 4) >
590 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
591 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
592 return true;
593 }
594 }
595 return false;
596}
597
598Fault
599X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
600{
601 assert(checkInterrupts(tc));
602 // These are all probably fairly uncommon, so we'll make them easier to
603 // check for.
604 if (pendingUnmaskableInt) {
605 if (pendingSmi) {
606 DPRINTF(LocalApic, "Generated SMI fault object.\n");
607 return new SystemManagementInterrupt();
608 } else if (pendingNmi) {
609 DPRINTF(LocalApic, "Generated NMI fault object.\n");
610 return new NonMaskableInterrupt(nmiVector);
611 } else if (pendingInit) {
612 DPRINTF(LocalApic, "Generated INIT fault object.\n");
613 return new InitInterrupt(initVector);
614 } else if (pendingStartup) {
615 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
616 return new StartupInterrupt(startupVector);
617 } else {
618 panic("pendingUnmaskableInt set, but no unmaskable "
619 "ints were pending.\n");
620 return NoFault;
621 }
622 } else if (pendingExtInt) {
623 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
624 return new ExternalInterrupt(extIntVector);
625 } else {
626 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
627 // The only thing left are fixed and lowest priority interrupts.
628 return new ExternalInterrupt(IRRV);
629 }
630}
631
632void
633X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
634{
635 assert(checkInterrupts(tc));
636 if (pendingUnmaskableInt) {
637 if (pendingSmi) {
638 DPRINTF(LocalApic, "SMI sent to core.\n");
639 pendingSmi = false;
640 } else if (pendingNmi) {
641 DPRINTF(LocalApic, "NMI sent to core.\n");
642 pendingNmi = false;
643 } else if (pendingInit) {
644 DPRINTF(LocalApic, "Init sent to core.\n");
645 pendingInit = false;
646 } else if (pendingStartup) {
647 DPRINTF(LocalApic, "SIPI sent to core.\n");
648 pendingStartup = false;
649 }
650 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
651 pendingUnmaskableInt = false;
652 } else if (pendingExtInt) {
653 pendingExtInt = false;
654 } else {
655 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
656 // Mark the interrupt as "in service".
657 ISRV = IRRV;
658 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
659 // Clear it out of the IRR.
660 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
661 updateIRRV();
662 }
663}
664
665X86ISA::Interrupts *
666X86LocalApicParams::create()
667{
668 return new X86ISA::Interrupts(this);
669}
|