1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71 shift = (shift + 1) % 8;
72 return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81 ApicRegIndex regNum;
82 paddr &= ~mask(3);
83 switch (paddr)
84 {
85 case 0x20:
86 regNum = APIC_ID;
87 break;
88 case 0x30:
89 regNum = APIC_VERSION;
90 break;
91 case 0x80:
92 regNum = APIC_TASK_PRIORITY;
93 break;
94 case 0x90:
95 regNum = APIC_ARBITRATION_PRIORITY;
96 break;
97 case 0xA0:
98 regNum = APIC_PROCESSOR_PRIORITY;
99 break;
100 case 0xB0:
101 regNum = APIC_EOI;
102 break;
103 case 0xD0:
104 regNum = APIC_LOGICAL_DESTINATION;
105 break;
106 case 0xE0:
107 regNum = APIC_DESTINATION_FORMAT;
108 break;
109 case 0xF0:
110 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111 break;
112 case 0x100:
113 case 0x108:
114 case 0x110:
115 case 0x118:
116 case 0x120:
117 case 0x128:
118 case 0x130:
119 case 0x138:
120 case 0x140:
121 case 0x148:
122 case 0x150:
123 case 0x158:
124 case 0x160:
125 case 0x168:
126 case 0x170:
127 case 0x178:
128 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129 break;
130 case 0x180:
131 case 0x188:
132 case 0x190:
133 case 0x198:
134 case 0x1A0:
135 case 0x1A8:
136 case 0x1B0:
137 case 0x1B8:
138 case 0x1C0:
139 case 0x1C8:
140 case 0x1D0:
141 case 0x1D8:
142 case 0x1E0:
143 case 0x1E8:
144 case 0x1F0:
145 case 0x1F8:
146 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147 break;
148 case 0x200:
149 case 0x208:
150 case 0x210:
151 case 0x218:
152 case 0x220:
153 case 0x228:
154 case 0x230:
155 case 0x238:
156 case 0x240:
157 case 0x248:
158 case 0x250:
159 case 0x258:
160 case 0x260:
161 case 0x268:
162 case 0x270:
163 case 0x278:
164 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165 break;
166 case 0x280:
167 regNum = APIC_ERROR_STATUS;
168 break;
169 case 0x300:
170 regNum = APIC_INTERRUPT_COMMAND_LOW;
171 break;
172 case 0x310:
173 regNum = APIC_INTERRUPT_COMMAND_HIGH;
174 break;
175 case 0x320:
176 regNum = APIC_LVT_TIMER;
177 break;
178 case 0x330:
179 regNum = APIC_LVT_THERMAL_SENSOR;
180 break;
181 case 0x340:
182 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183 break;
184 case 0x350:
185 regNum = APIC_LVT_LINT0;
186 break;
187 case 0x360:
188 regNum = APIC_LVT_LINT1;
189 break;
190 case 0x370:
191 regNum = APIC_LVT_ERROR;
192 break;
193 case 0x380:
194 regNum = APIC_INITIAL_COUNT;
195 break;
196 case 0x390:
197 regNum = APIC_CURRENT_COUNT;
198 break;
199 case 0x3E0:
200 regNum = APIC_DIVIDE_CONFIGURATION;
201 break;
202 default:
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr);
205 break;
206 }
207 return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214 Addr offset = pkt->getAddr() - pioAddr;
215 //Make sure we're at least only accessing one register.
216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 return latency;
225}
226
227Tick
228X86ISA::Interrupts::write(PacketPtr pkt)
229{
230 Addr offset = pkt->getAddr() - pioAddr;
231 //Make sure we're at least only accessing one register.
232 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
233 panic("Accessed more than one register at a time in the APIC!\n");
234 ApicRegIndex reg = decodeAddr(offset);
235 uint32_t val = regs[reg];
236 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
237 DPRINTF(LocalApic,
238 "Writing Local APIC register %d at offset %#x as %#x.\n",
239 reg, offset, gtoh(val));
240 setReg(reg, gtoh(val));
241 return latency;
242}
243
244Tick
245X86ISA::Interrupts::recvMessage(PacketPtr pkt)
246{
247 uint8_t id = 0;
248 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
249 assert(pkt->cmd == MemCmd::MessageReq);
250 switch(offset)
251 {
252 case 0:
253 {
254 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
255 uint8_t vector = message.vector;
256 DPRINTF(LocalApic,
257 "Got Trigger Interrupt message with vector %#x.\n",
258 vector);
259 // Make sure we're really supposed to get this.
260 assert((message.destMode == 0 && message.destination == id) ||
261 (bits((int)message.destination, id)));
262
263 /*
264 * Fixed and lowest-priority delivery mode interrupts are handled
265 * using the IRR/ISR registers, checking against the TPR, etc.
266 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
267 */
268 if (message.deliveryMode == DeliveryMode::Fixed ||
269 message.deliveryMode == DeliveryMode::LowestPriority) {
270 DPRINTF(LocalApic, "Interrupt is an %s.\n",
271 DeliveryMode::names[message.deliveryMode]);
272 // Queue up the interrupt in the IRR.
273 if (vector > IRRV)
274 IRRV = vector;
275 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
276 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
277 if (message.trigger) {
278 // Level triggered.
279 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
280 } else {
281 // Edge triggered.
282 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
283 }
284 }
285 } else if (!DeliveryMode::isReserved(message.deliveryMode)) {
286 DPRINTF(LocalApic, "Interrupt is an %s.\n",
287 DeliveryMode::names[message.deliveryMode]);
288 if (message.deliveryMode == DeliveryMode::SMI &&
289 !pendingSmi) {
290 pendingUnmaskableInt = pendingSmi = true;
291 smiMessage = message;
292 } else if (message.deliveryMode == DeliveryMode::NMI &&
293 !pendingNmi) {
294 pendingUnmaskableInt = pendingNmi = true;
295 nmiMessage = message;
296 } else if (message.deliveryMode == DeliveryMode::ExtInt &&
297 !pendingExtInt) {
298 pendingExtInt = true;
299 extIntMessage = message;
300 } else if (message.deliveryMode == DeliveryMode::INIT &&
301 !pendingInit) {
302 pendingUnmaskableInt = pendingInit = true;
303 initMessage = message;
304 }
305 }
306 }
307 break;
308 default:
309 panic("Local apic got unknown interrupt message at offset %#x.\n",
310 offset);
311 break;
312 }
313 delete pkt->req;
314 delete pkt;
315 return latency;
316}
317
318
319uint32_t
320X86ISA::Interrupts::readReg(ApicRegIndex reg)
321{
322 if (reg >= APIC_TRIGGER_MODE(0) &&
323 reg <= APIC_TRIGGER_MODE(15)) {
324 panic("Local APIC Trigger Mode registers are unimplemented.\n");
325 }
326 switch (reg) {
327 case APIC_ARBITRATION_PRIORITY:
328 panic("Local APIC Arbitration Priority register unimplemented.\n");
329 break;
330 case APIC_PROCESSOR_PRIORITY:
331 panic("Local APIC Processor Priority register unimplemented.\n");
332 break;
333 case APIC_EOI:
334 panic("Local APIC EOI register unimplemented.\n");
335 break;
336 case APIC_ERROR_STATUS:
337 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
338 break;
339 case APIC_INTERRUPT_COMMAND_LOW:
340 panic("Local APIC Interrupt Command low"
341 " register unimplemented.\n");
342 break;
343 case APIC_INTERRUPT_COMMAND_HIGH:
344 panic("Local APIC Interrupt Command high"
345 " register unimplemented.\n");
346 break;
347 case APIC_CURRENT_COUNT:
348 {
349 assert(clock);
350 uint32_t val = regs[reg] - curTick / clock;
351 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
352 return val;
353 }
354 default:
355 break;
356 }
357 return regs[reg];
358}
359
360void
361X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
362{
363 uint32_t newVal = val;
364 if (reg >= APIC_IN_SERVICE(0) &&
365 reg <= APIC_IN_SERVICE(15)) {
366 panic("Local APIC In-Service registers are unimplemented.\n");
367 }
368 if (reg >= APIC_TRIGGER_MODE(0) &&
369 reg <= APIC_TRIGGER_MODE(15)) {
370 panic("Local APIC Trigger Mode registers are unimplemented.\n");
371 }
372 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
373 reg <= APIC_INTERRUPT_REQUEST(15)) {
374 panic("Local APIC Interrupt Request registers "
375 "are unimplemented.\n");
376 }
377 switch (reg) {
378 case APIC_ID:
379 newVal = val & 0xFF;
380 break;
381 case APIC_VERSION:
382 // The Local APIC Version register is read only.
383 return;
384 case APIC_TASK_PRIORITY:
385 newVal = val & 0xFF;
386 break;
387 case APIC_ARBITRATION_PRIORITY:
388 panic("Local APIC Arbitration Priority register unimplemented.\n");
389 break;
390 case APIC_PROCESSOR_PRIORITY:
391 panic("Local APIC Processor Priority register unimplemented.\n");
392 break;
393 case APIC_EOI:
394 panic("Local APIC EOI register unimplemented.\n");
395 break;
396 case APIC_LOGICAL_DESTINATION:
397 newVal = val & 0xFF000000;
398 break;
399 case APIC_DESTINATION_FORMAT:
400 newVal = val | 0x0FFFFFFF;
401 break;
402 case APIC_SPURIOUS_INTERRUPT_VECTOR:
403 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
404 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
405 if (val & (1 << 9))
406 warn("Focus processor checking not implemented.\n");
407 break;
408 case APIC_ERROR_STATUS:
409 {
410 if (regs[APIC_INTERNAL_STATE] & 0x1) {
411 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
412 newVal = 0;
413 } else {
414 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
415 return;
416 }
417
418 }
419 break;
420 case APIC_INTERRUPT_COMMAND_LOW:
421 panic("Local APIC Interrupt Command low"
422 " register unimplemented.\n");
423 break;
424 case APIC_INTERRUPT_COMMAND_HIGH:
425 panic("Local APIC Interrupt Command high"
426 " register unimplemented.\n");
427 break;
428 case APIC_LVT_TIMER:
429 case APIC_LVT_THERMAL_SENSOR:
430 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
431 case APIC_LVT_LINT0:
432 case APIC_LVT_LINT1:
433 case APIC_LVT_ERROR:
434 {
435 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
436 newVal = (val & ~readOnlyMask) |
437 (regs[reg] & readOnlyMask);
438 }
439 break;
440 case APIC_INITIAL_COUNT:
441 {
442 assert(clock);
443 newVal = bits(val, 31, 0);
444 uint32_t newCount = newVal *
445 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
446 regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
447 // Find out how long a "tick" of the timer should take.
448 Tick timerTick = 16 * clock;
449 // Schedule on the edge of the next tick plus the new count.
450 Tick offset = curTick % timerTick;
451 if (offset) {
452 reschedule(apicTimerEvent,
453 curTick + (newCount + 1) * timerTick - offset, true);
454 } else {
455 reschedule(apicTimerEvent,
456 curTick + newCount * timerTick, true);
457 }
458 }
459 break;
460 case APIC_CURRENT_COUNT:
461 //Local APIC Current Count register is read only.
462 return;
463 case APIC_DIVIDE_CONFIGURATION:
464 newVal = val & 0xB;
465 break;
466 default:
467 break;
468 }
469 regs[reg] = newVal;
470 return;
471}
472
473bool
474X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const
475{
476 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
| 1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71 shift = (shift + 1) % 8;
72 return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81 ApicRegIndex regNum;
82 paddr &= ~mask(3);
83 switch (paddr)
84 {
85 case 0x20:
86 regNum = APIC_ID;
87 break;
88 case 0x30:
89 regNum = APIC_VERSION;
90 break;
91 case 0x80:
92 regNum = APIC_TASK_PRIORITY;
93 break;
94 case 0x90:
95 regNum = APIC_ARBITRATION_PRIORITY;
96 break;
97 case 0xA0:
98 regNum = APIC_PROCESSOR_PRIORITY;
99 break;
100 case 0xB0:
101 regNum = APIC_EOI;
102 break;
103 case 0xD0:
104 regNum = APIC_LOGICAL_DESTINATION;
105 break;
106 case 0xE0:
107 regNum = APIC_DESTINATION_FORMAT;
108 break;
109 case 0xF0:
110 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111 break;
112 case 0x100:
113 case 0x108:
114 case 0x110:
115 case 0x118:
116 case 0x120:
117 case 0x128:
118 case 0x130:
119 case 0x138:
120 case 0x140:
121 case 0x148:
122 case 0x150:
123 case 0x158:
124 case 0x160:
125 case 0x168:
126 case 0x170:
127 case 0x178:
128 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129 break;
130 case 0x180:
131 case 0x188:
132 case 0x190:
133 case 0x198:
134 case 0x1A0:
135 case 0x1A8:
136 case 0x1B0:
137 case 0x1B8:
138 case 0x1C0:
139 case 0x1C8:
140 case 0x1D0:
141 case 0x1D8:
142 case 0x1E0:
143 case 0x1E8:
144 case 0x1F0:
145 case 0x1F8:
146 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147 break;
148 case 0x200:
149 case 0x208:
150 case 0x210:
151 case 0x218:
152 case 0x220:
153 case 0x228:
154 case 0x230:
155 case 0x238:
156 case 0x240:
157 case 0x248:
158 case 0x250:
159 case 0x258:
160 case 0x260:
161 case 0x268:
162 case 0x270:
163 case 0x278:
164 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165 break;
166 case 0x280:
167 regNum = APIC_ERROR_STATUS;
168 break;
169 case 0x300:
170 regNum = APIC_INTERRUPT_COMMAND_LOW;
171 break;
172 case 0x310:
173 regNum = APIC_INTERRUPT_COMMAND_HIGH;
174 break;
175 case 0x320:
176 regNum = APIC_LVT_TIMER;
177 break;
178 case 0x330:
179 regNum = APIC_LVT_THERMAL_SENSOR;
180 break;
181 case 0x340:
182 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183 break;
184 case 0x350:
185 regNum = APIC_LVT_LINT0;
186 break;
187 case 0x360:
188 regNum = APIC_LVT_LINT1;
189 break;
190 case 0x370:
191 regNum = APIC_LVT_ERROR;
192 break;
193 case 0x380:
194 regNum = APIC_INITIAL_COUNT;
195 break;
196 case 0x390:
197 regNum = APIC_CURRENT_COUNT;
198 break;
199 case 0x3E0:
200 regNum = APIC_DIVIDE_CONFIGURATION;
201 break;
202 default:
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr);
205 break;
206 }
207 return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214 Addr offset = pkt->getAddr() - pioAddr;
215 //Make sure we're at least only accessing one register.
216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 return latency;
225}
226
227Tick
228X86ISA::Interrupts::write(PacketPtr pkt)
229{
230 Addr offset = pkt->getAddr() - pioAddr;
231 //Make sure we're at least only accessing one register.
232 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
233 panic("Accessed more than one register at a time in the APIC!\n");
234 ApicRegIndex reg = decodeAddr(offset);
235 uint32_t val = regs[reg];
236 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
237 DPRINTF(LocalApic,
238 "Writing Local APIC register %d at offset %#x as %#x.\n",
239 reg, offset, gtoh(val));
240 setReg(reg, gtoh(val));
241 return latency;
242}
243
244Tick
245X86ISA::Interrupts::recvMessage(PacketPtr pkt)
246{
247 uint8_t id = 0;
248 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
249 assert(pkt->cmd == MemCmd::MessageReq);
250 switch(offset)
251 {
252 case 0:
253 {
254 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
255 uint8_t vector = message.vector;
256 DPRINTF(LocalApic,
257 "Got Trigger Interrupt message with vector %#x.\n",
258 vector);
259 // Make sure we're really supposed to get this.
260 assert((message.destMode == 0 && message.destination == id) ||
261 (bits((int)message.destination, id)));
262
263 /*
264 * Fixed and lowest-priority delivery mode interrupts are handled
265 * using the IRR/ISR registers, checking against the TPR, etc.
266 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
267 */
268 if (message.deliveryMode == DeliveryMode::Fixed ||
269 message.deliveryMode == DeliveryMode::LowestPriority) {
270 DPRINTF(LocalApic, "Interrupt is an %s.\n",
271 DeliveryMode::names[message.deliveryMode]);
272 // Queue up the interrupt in the IRR.
273 if (vector > IRRV)
274 IRRV = vector;
275 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
276 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
277 if (message.trigger) {
278 // Level triggered.
279 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
280 } else {
281 // Edge triggered.
282 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
283 }
284 }
285 } else if (!DeliveryMode::isReserved(message.deliveryMode)) {
286 DPRINTF(LocalApic, "Interrupt is an %s.\n",
287 DeliveryMode::names[message.deliveryMode]);
288 if (message.deliveryMode == DeliveryMode::SMI &&
289 !pendingSmi) {
290 pendingUnmaskableInt = pendingSmi = true;
291 smiMessage = message;
292 } else if (message.deliveryMode == DeliveryMode::NMI &&
293 !pendingNmi) {
294 pendingUnmaskableInt = pendingNmi = true;
295 nmiMessage = message;
296 } else if (message.deliveryMode == DeliveryMode::ExtInt &&
297 !pendingExtInt) {
298 pendingExtInt = true;
299 extIntMessage = message;
300 } else if (message.deliveryMode == DeliveryMode::INIT &&
301 !pendingInit) {
302 pendingUnmaskableInt = pendingInit = true;
303 initMessage = message;
304 }
305 }
306 }
307 break;
308 default:
309 panic("Local apic got unknown interrupt message at offset %#x.\n",
310 offset);
311 break;
312 }
313 delete pkt->req;
314 delete pkt;
315 return latency;
316}
317
318
319uint32_t
320X86ISA::Interrupts::readReg(ApicRegIndex reg)
321{
322 if (reg >= APIC_TRIGGER_MODE(0) &&
323 reg <= APIC_TRIGGER_MODE(15)) {
324 panic("Local APIC Trigger Mode registers are unimplemented.\n");
325 }
326 switch (reg) {
327 case APIC_ARBITRATION_PRIORITY:
328 panic("Local APIC Arbitration Priority register unimplemented.\n");
329 break;
330 case APIC_PROCESSOR_PRIORITY:
331 panic("Local APIC Processor Priority register unimplemented.\n");
332 break;
333 case APIC_EOI:
334 panic("Local APIC EOI register unimplemented.\n");
335 break;
336 case APIC_ERROR_STATUS:
337 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
338 break;
339 case APIC_INTERRUPT_COMMAND_LOW:
340 panic("Local APIC Interrupt Command low"
341 " register unimplemented.\n");
342 break;
343 case APIC_INTERRUPT_COMMAND_HIGH:
344 panic("Local APIC Interrupt Command high"
345 " register unimplemented.\n");
346 break;
347 case APIC_CURRENT_COUNT:
348 {
349 assert(clock);
350 uint32_t val = regs[reg] - curTick / clock;
351 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
352 return val;
353 }
354 default:
355 break;
356 }
357 return regs[reg];
358}
359
360void
361X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
362{
363 uint32_t newVal = val;
364 if (reg >= APIC_IN_SERVICE(0) &&
365 reg <= APIC_IN_SERVICE(15)) {
366 panic("Local APIC In-Service registers are unimplemented.\n");
367 }
368 if (reg >= APIC_TRIGGER_MODE(0) &&
369 reg <= APIC_TRIGGER_MODE(15)) {
370 panic("Local APIC Trigger Mode registers are unimplemented.\n");
371 }
372 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
373 reg <= APIC_INTERRUPT_REQUEST(15)) {
374 panic("Local APIC Interrupt Request registers "
375 "are unimplemented.\n");
376 }
377 switch (reg) {
378 case APIC_ID:
379 newVal = val & 0xFF;
380 break;
381 case APIC_VERSION:
382 // The Local APIC Version register is read only.
383 return;
384 case APIC_TASK_PRIORITY:
385 newVal = val & 0xFF;
386 break;
387 case APIC_ARBITRATION_PRIORITY:
388 panic("Local APIC Arbitration Priority register unimplemented.\n");
389 break;
390 case APIC_PROCESSOR_PRIORITY:
391 panic("Local APIC Processor Priority register unimplemented.\n");
392 break;
393 case APIC_EOI:
394 panic("Local APIC EOI register unimplemented.\n");
395 break;
396 case APIC_LOGICAL_DESTINATION:
397 newVal = val & 0xFF000000;
398 break;
399 case APIC_DESTINATION_FORMAT:
400 newVal = val | 0x0FFFFFFF;
401 break;
402 case APIC_SPURIOUS_INTERRUPT_VECTOR:
403 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
404 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
405 if (val & (1 << 9))
406 warn("Focus processor checking not implemented.\n");
407 break;
408 case APIC_ERROR_STATUS:
409 {
410 if (regs[APIC_INTERNAL_STATE] & 0x1) {
411 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
412 newVal = 0;
413 } else {
414 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
415 return;
416 }
417
418 }
419 break;
420 case APIC_INTERRUPT_COMMAND_LOW:
421 panic("Local APIC Interrupt Command low"
422 " register unimplemented.\n");
423 break;
424 case APIC_INTERRUPT_COMMAND_HIGH:
425 panic("Local APIC Interrupt Command high"
426 " register unimplemented.\n");
427 break;
428 case APIC_LVT_TIMER:
429 case APIC_LVT_THERMAL_SENSOR:
430 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
431 case APIC_LVT_LINT0:
432 case APIC_LVT_LINT1:
433 case APIC_LVT_ERROR:
434 {
435 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
436 newVal = (val & ~readOnlyMask) |
437 (regs[reg] & readOnlyMask);
438 }
439 break;
440 case APIC_INITIAL_COUNT:
441 {
442 assert(clock);
443 newVal = bits(val, 31, 0);
444 uint32_t newCount = newVal *
445 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
446 regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
447 // Find out how long a "tick" of the timer should take.
448 Tick timerTick = 16 * clock;
449 // Schedule on the edge of the next tick plus the new count.
450 Tick offset = curTick % timerTick;
451 if (offset) {
452 reschedule(apicTimerEvent,
453 curTick + (newCount + 1) * timerTick - offset, true);
454 } else {
455 reschedule(apicTimerEvent,
456 curTick + newCount * timerTick, true);
457 }
458 }
459 break;
460 case APIC_CURRENT_COUNT:
461 //Local APIC Current Count register is read only.
462 return;
463 case APIC_DIVIDE_CONFIGURATION:
464 newVal = val & 0xB;
465 break;
466 default:
467 break;
468 }
469 regs[reg] = newVal;
470 return;
471}
472
473bool
474X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const
475{
476 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
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