1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/interrupts.hh"
53
54#include <memory>
55
56#include "arch/x86/intmessage.hh"
57#include "arch/x86/regs/apic.hh"
58#include "cpu/base.hh"
59#include "debug/LocalApic.hh"
60#include "dev/x86/i82094aa.hh"
61#include "dev/x86/pc.hh"
62#include "dev/x86/south_bridge.hh"
63#include "mem/packet_access.hh"
64#include "sim/full_system.hh"
65#include "sim/system.hh"
66
67int
68divideFromConf(uint32_t conf)
69{
70 // This figures out what division we want from the division configuration
71 // register in the local APIC. The encoding is a little odd but it can
72 // be deciphered fairly easily.
73 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
74 shift = (shift + 1) % 8;
75 return 1 << shift;
76}
77
78namespace X86ISA
79{
80
81ApicRegIndex
82decodeAddr(Addr paddr)
83{
84 ApicRegIndex regNum;
85 paddr &= ~mask(3);
86 switch (paddr)
87 {
88 case 0x20:
89 regNum = APIC_ID;
90 break;
91 case 0x30:
92 regNum = APIC_VERSION;
93 break;
94 case 0x80:
95 regNum = APIC_TASK_PRIORITY;
96 break;
97 case 0x90:
98 regNum = APIC_ARBITRATION_PRIORITY;
99 break;
100 case 0xA0:
101 regNum = APIC_PROCESSOR_PRIORITY;
102 break;
103 case 0xB0:
104 regNum = APIC_EOI;
105 break;
106 case 0xD0:
107 regNum = APIC_LOGICAL_DESTINATION;
108 break;
109 case 0xE0:
110 regNum = APIC_DESTINATION_FORMAT;
111 break;
112 case 0xF0:
113 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
114 break;
115 case 0x100:
116 case 0x110:
117 case 0x120:
118 case 0x130:
119 case 0x140:
120 case 0x150:
121 case 0x160:
122 case 0x170:
123 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
124 break;
125 case 0x180:
126 case 0x190:
127 case 0x1A0:
128 case 0x1B0:
129 case 0x1C0:
130 case 0x1D0:
131 case 0x1E0:
132 case 0x1F0:
133 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
134 break;
135 case 0x200:
136 case 0x210:
137 case 0x220:
138 case 0x230:
139 case 0x240:
140 case 0x250:
141 case 0x260:
142 case 0x270:
143 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
144 break;
145 case 0x280:
146 regNum = APIC_ERROR_STATUS;
147 break;
148 case 0x300:
149 regNum = APIC_INTERRUPT_COMMAND_LOW;
150 break;
151 case 0x310:
152 regNum = APIC_INTERRUPT_COMMAND_HIGH;
153 break;
154 case 0x320:
155 regNum = APIC_LVT_TIMER;
156 break;
157 case 0x330:
158 regNum = APIC_LVT_THERMAL_SENSOR;
159 break;
160 case 0x340:
161 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
162 break;
163 case 0x350:
164 regNum = APIC_LVT_LINT0;
165 break;
166 case 0x360:
167 regNum = APIC_LVT_LINT1;
168 break;
169 case 0x370:
170 regNum = APIC_LVT_ERROR;
171 break;
172 case 0x380:
173 regNum = APIC_INITIAL_COUNT;
174 break;
175 case 0x390:
176 regNum = APIC_CURRENT_COUNT;
177 break;
178 case 0x3E0:
179 regNum = APIC_DIVIDE_CONFIGURATION;
180 break;
181 default:
182 // A reserved register field.
183 panic("Accessed reserved register field %#x.\n", paddr);
184 break;
185 }
186 return regNum;
187}
188}
189
190Tick
191X86ISA::Interrupts::read(PacketPtr pkt)
192{
193 Addr offset = pkt->getAddr() - pioAddr;
194 // Make sure we're at least only accessing one register.
195 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
196 panic("Accessed more than one register at a time in the APIC!\n");
197 ApicRegIndex reg = decodeAddr(offset);
198 uint32_t val = htog(readReg(reg));
199 DPRINTF(LocalApic,
200 "Reading Local APIC register %d at offset %#x as %#x.\n",
201 reg, offset, val);
202 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
203 pkt->makeAtomicResponse();
204 return pioDelay;
205}
206
207Tick
208X86ISA::Interrupts::write(PacketPtr pkt)
209{
210 Addr offset = pkt->getAddr() - pioAddr;
211 // Make sure we're at least only accessing one register.
212 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
213 panic("Accessed more than one register at a time in the APIC!\n");
214 ApicRegIndex reg = decodeAddr(offset);
215 uint32_t val = regs[reg];
216 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
217 DPRINTF(LocalApic,
218 "Writing Local APIC register %d at offset %#x as %#x.\n",
219 reg, offset, gtoh(val));
220 setReg(reg, gtoh(val));
221 pkt->makeAtomicResponse();
222 return pioDelay;
223}
224void
225X86ISA::Interrupts::requestInterrupt(uint8_t vector,
226 uint8_t deliveryMode, bool level)
227{
228 /*
229 * Fixed and lowest-priority delivery mode interrupts are handled
230 * using the IRR/ISR registers, checking against the TPR, etc.
231 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
232 */
233 if (deliveryMode == DeliveryMode::Fixed ||
234 deliveryMode == DeliveryMode::LowestPriority) {
235 DPRINTF(LocalApic, "Interrupt is an %s.\n",
236 DeliveryMode::names[deliveryMode]);
237 // Queue up the interrupt in the IRR.
238 if (vector > IRRV)
239 IRRV = vector;
240 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
241 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
242 if (level) {
243 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
244 } else {
245 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
246 }
247 }
248 } else if (!DeliveryMode::isReserved(deliveryMode)) {
249 DPRINTF(LocalApic, "Interrupt is an %s.\n",
250 DeliveryMode::names[deliveryMode]);
251 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
252 pendingUnmaskableInt = pendingSmi = true;
253 smiVector = vector;
254 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
255 pendingUnmaskableInt = pendingNmi = true;
256 nmiVector = vector;
257 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
258 pendingExtInt = true;
259 extIntVector = vector;
260 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
261 pendingUnmaskableInt = pendingInit = true;
262 initVector = vector;
263 } else if (deliveryMode == DeliveryMode::SIPI &&
264 !pendingStartup && !startedUp) {
265 pendingUnmaskableInt = pendingStartup = true;
266 startupVector = vector;
267 }
268 }
269 if (FullSystem)
270 cpu->wakeup(0);
271}
272
273
274void
275X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
276{
277 assert(newCPU);
278 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
279 panic("Local APICs can't be moved between CPUs"
280 " with different IDs.\n");
281 }
282 cpu = newCPU;
283 initialApicId = cpu->cpuId();
284 regs[APIC_ID] = (initialApicId << 24);
285 pioAddr = x86LocalAPICAddress(initialApicId, 0);
286}
287
288
289void
290X86ISA::Interrupts::init()
291{
292 //
293 // The local apic must register its address ranges on both its pio
294 // port via the basicpiodevice(piodevice) init() function and its
295 // int port that it inherited from IntDevice. Note IntDevice is
296 // not a SimObject itself.
297 //
298 PioDevice::init();
299 IntDevice::init();
300
301 // the slave port has a range so inform the connected master
302 intSlavePort.sendRangeChange();
303}
304
305
306Tick
307X86ISA::Interrupts::recvMessage(PacketPtr pkt)
308{
309 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
310 assert(pkt->cmd == MemCmd::MessageReq);
311 switch(offset)
312 {
313 case 0:
314 {
315 TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
316 DPRINTF(LocalApic,
317 "Got Trigger Interrupt message with vector %#x.\n",
318 message.vector);
319
320 requestInterrupt(message.vector,
321 message.deliveryMode, message.trigger);
322 }
323 break;
324 default:
325 panic("Local apic got unknown interrupt message at offset %#x.\n",
326 offset);
327 break;
328 }
329 pkt->makeAtomicResponse();
330 return pioDelay;
331}
332
333
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/interrupts.hh"
53
54#include <memory>
55
56#include "arch/x86/intmessage.hh"
57#include "arch/x86/regs/apic.hh"
58#include "cpu/base.hh"
59#include "debug/LocalApic.hh"
60#include "dev/x86/i82094aa.hh"
61#include "dev/x86/pc.hh"
62#include "dev/x86/south_bridge.hh"
63#include "mem/packet_access.hh"
64#include "sim/full_system.hh"
65#include "sim/system.hh"
66
67int
68divideFromConf(uint32_t conf)
69{
70 // This figures out what division we want from the division configuration
71 // register in the local APIC. The encoding is a little odd but it can
72 // be deciphered fairly easily.
73 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
74 shift = (shift + 1) % 8;
75 return 1 << shift;
76}
77
78namespace X86ISA
79{
80
81ApicRegIndex
82decodeAddr(Addr paddr)
83{
84 ApicRegIndex regNum;
85 paddr &= ~mask(3);
86 switch (paddr)
87 {
88 case 0x20:
89 regNum = APIC_ID;
90 break;
91 case 0x30:
92 regNum = APIC_VERSION;
93 break;
94 case 0x80:
95 regNum = APIC_TASK_PRIORITY;
96 break;
97 case 0x90:
98 regNum = APIC_ARBITRATION_PRIORITY;
99 break;
100 case 0xA0:
101 regNum = APIC_PROCESSOR_PRIORITY;
102 break;
103 case 0xB0:
104 regNum = APIC_EOI;
105 break;
106 case 0xD0:
107 regNum = APIC_LOGICAL_DESTINATION;
108 break;
109 case 0xE0:
110 regNum = APIC_DESTINATION_FORMAT;
111 break;
112 case 0xF0:
113 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
114 break;
115 case 0x100:
116 case 0x110:
117 case 0x120:
118 case 0x130:
119 case 0x140:
120 case 0x150:
121 case 0x160:
122 case 0x170:
123 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
124 break;
125 case 0x180:
126 case 0x190:
127 case 0x1A0:
128 case 0x1B0:
129 case 0x1C0:
130 case 0x1D0:
131 case 0x1E0:
132 case 0x1F0:
133 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
134 break;
135 case 0x200:
136 case 0x210:
137 case 0x220:
138 case 0x230:
139 case 0x240:
140 case 0x250:
141 case 0x260:
142 case 0x270:
143 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
144 break;
145 case 0x280:
146 regNum = APIC_ERROR_STATUS;
147 break;
148 case 0x300:
149 regNum = APIC_INTERRUPT_COMMAND_LOW;
150 break;
151 case 0x310:
152 regNum = APIC_INTERRUPT_COMMAND_HIGH;
153 break;
154 case 0x320:
155 regNum = APIC_LVT_TIMER;
156 break;
157 case 0x330:
158 regNum = APIC_LVT_THERMAL_SENSOR;
159 break;
160 case 0x340:
161 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
162 break;
163 case 0x350:
164 regNum = APIC_LVT_LINT0;
165 break;
166 case 0x360:
167 regNum = APIC_LVT_LINT1;
168 break;
169 case 0x370:
170 regNum = APIC_LVT_ERROR;
171 break;
172 case 0x380:
173 regNum = APIC_INITIAL_COUNT;
174 break;
175 case 0x390:
176 regNum = APIC_CURRENT_COUNT;
177 break;
178 case 0x3E0:
179 regNum = APIC_DIVIDE_CONFIGURATION;
180 break;
181 default:
182 // A reserved register field.
183 panic("Accessed reserved register field %#x.\n", paddr);
184 break;
185 }
186 return regNum;
187}
188}
189
190Tick
191X86ISA::Interrupts::read(PacketPtr pkt)
192{
193 Addr offset = pkt->getAddr() - pioAddr;
194 // Make sure we're at least only accessing one register.
195 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
196 panic("Accessed more than one register at a time in the APIC!\n");
197 ApicRegIndex reg = decodeAddr(offset);
198 uint32_t val = htog(readReg(reg));
199 DPRINTF(LocalApic,
200 "Reading Local APIC register %d at offset %#x as %#x.\n",
201 reg, offset, val);
202 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
203 pkt->makeAtomicResponse();
204 return pioDelay;
205}
206
207Tick
208X86ISA::Interrupts::write(PacketPtr pkt)
209{
210 Addr offset = pkt->getAddr() - pioAddr;
211 // Make sure we're at least only accessing one register.
212 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
213 panic("Accessed more than one register at a time in the APIC!\n");
214 ApicRegIndex reg = decodeAddr(offset);
215 uint32_t val = regs[reg];
216 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
217 DPRINTF(LocalApic,
218 "Writing Local APIC register %d at offset %#x as %#x.\n",
219 reg, offset, gtoh(val));
220 setReg(reg, gtoh(val));
221 pkt->makeAtomicResponse();
222 return pioDelay;
223}
224void
225X86ISA::Interrupts::requestInterrupt(uint8_t vector,
226 uint8_t deliveryMode, bool level)
227{
228 /*
229 * Fixed and lowest-priority delivery mode interrupts are handled
230 * using the IRR/ISR registers, checking against the TPR, etc.
231 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
232 */
233 if (deliveryMode == DeliveryMode::Fixed ||
234 deliveryMode == DeliveryMode::LowestPriority) {
235 DPRINTF(LocalApic, "Interrupt is an %s.\n",
236 DeliveryMode::names[deliveryMode]);
237 // Queue up the interrupt in the IRR.
238 if (vector > IRRV)
239 IRRV = vector;
240 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
241 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
242 if (level) {
243 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
244 } else {
245 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
246 }
247 }
248 } else if (!DeliveryMode::isReserved(deliveryMode)) {
249 DPRINTF(LocalApic, "Interrupt is an %s.\n",
250 DeliveryMode::names[deliveryMode]);
251 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
252 pendingUnmaskableInt = pendingSmi = true;
253 smiVector = vector;
254 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
255 pendingUnmaskableInt = pendingNmi = true;
256 nmiVector = vector;
257 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
258 pendingExtInt = true;
259 extIntVector = vector;
260 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
261 pendingUnmaskableInt = pendingInit = true;
262 initVector = vector;
263 } else if (deliveryMode == DeliveryMode::SIPI &&
264 !pendingStartup && !startedUp) {
265 pendingUnmaskableInt = pendingStartup = true;
266 startupVector = vector;
267 }
268 }
269 if (FullSystem)
270 cpu->wakeup(0);
271}
272
273
274void
275X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
276{
277 assert(newCPU);
278 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
279 panic("Local APICs can't be moved between CPUs"
280 " with different IDs.\n");
281 }
282 cpu = newCPU;
283 initialApicId = cpu->cpuId();
284 regs[APIC_ID] = (initialApicId << 24);
285 pioAddr = x86LocalAPICAddress(initialApicId, 0);
286}
287
288
289void
290X86ISA::Interrupts::init()
291{
292 //
293 // The local apic must register its address ranges on both its pio
294 // port via the basicpiodevice(piodevice) init() function and its
295 // int port that it inherited from IntDevice. Note IntDevice is
296 // not a SimObject itself.
297 //
298 PioDevice::init();
299 IntDevice::init();
300
301 // the slave port has a range so inform the connected master
302 intSlavePort.sendRangeChange();
303}
304
305
306Tick
307X86ISA::Interrupts::recvMessage(PacketPtr pkt)
308{
309 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
310 assert(pkt->cmd == MemCmd::MessageReq);
311 switch(offset)
312 {
313 case 0:
314 {
315 TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
316 DPRINTF(LocalApic,
317 "Got Trigger Interrupt message with vector %#x.\n",
318 message.vector);
319
320 requestInterrupt(message.vector,
321 message.deliveryMode, message.trigger);
322 }
323 break;
324 default:
325 panic("Local apic got unknown interrupt message at offset %#x.\n",
326 offset);
327 break;
328 }
329 pkt->makeAtomicResponse();
330 return pioDelay;
331}
332
333
|
347}
348
349
350AddrRangeList
351X86ISA::Interrupts::getAddrRanges() const
352{
353 assert(cpu);
354 AddrRangeList ranges;
355 ranges.push_back(RangeSize(pioAddr, PageBytes));
356 return ranges;
357}
358
359
360AddrRangeList
361X86ISA::Interrupts::getIntAddrRange() const
362{
363 AddrRangeList ranges;
364 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
365 x86InterruptAddress(initialApicId, 0) +
366 PhysAddrAPICRangeSize));
367 return ranges;
368}
369
370
371uint32_t
372X86ISA::Interrupts::readReg(ApicRegIndex reg)
373{
374 if (reg >= APIC_TRIGGER_MODE(0) &&
375 reg <= APIC_TRIGGER_MODE(15)) {
376 panic("Local APIC Trigger Mode registers are unimplemented.\n");
377 }
378 switch (reg) {
379 case APIC_ARBITRATION_PRIORITY:
380 panic("Local APIC Arbitration Priority register unimplemented.\n");
381 break;
382 case APIC_PROCESSOR_PRIORITY:
383 panic("Local APIC Processor Priority register unimplemented.\n");
384 break;
385 case APIC_ERROR_STATUS:
386 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
387 break;
388 case APIC_CURRENT_COUNT:
389 {
390 if (apicTimerEvent.scheduled()) {
391 // Compute how many m5 ticks happen per count.
392 uint64_t ticksPerCount = clockPeriod() *
393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
394 // Compute how many m5 ticks are left.
395 uint64_t val = apicTimerEvent.when() - curTick();
396 // Turn that into a count.
397 val = (val + ticksPerCount - 1) / ticksPerCount;
398 return val;
399 } else {
400 return 0;
401 }
402 }
403 default:
404 break;
405 }
406 return regs[reg];
407}
408
409void
410X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
411{
412 uint32_t newVal = val;
413 if (reg >= APIC_IN_SERVICE(0) &&
414 reg <= APIC_IN_SERVICE(15)) {
415 panic("Local APIC In-Service registers are unimplemented.\n");
416 }
417 if (reg >= APIC_TRIGGER_MODE(0) &&
418 reg <= APIC_TRIGGER_MODE(15)) {
419 panic("Local APIC Trigger Mode registers are unimplemented.\n");
420 }
421 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
422 reg <= APIC_INTERRUPT_REQUEST(15)) {
423 panic("Local APIC Interrupt Request registers "
424 "are unimplemented.\n");
425 }
426 switch (reg) {
427 case APIC_ID:
428 newVal = val & 0xFF;
429 break;
430 case APIC_VERSION:
431 // The Local APIC Version register is read only.
432 return;
433 case APIC_TASK_PRIORITY:
434 newVal = val & 0xFF;
435 break;
436 case APIC_ARBITRATION_PRIORITY:
437 panic("Local APIC Arbitration Priority register unimplemented.\n");
438 break;
439 case APIC_PROCESSOR_PRIORITY:
440 panic("Local APIC Processor Priority register unimplemented.\n");
441 break;
442 case APIC_EOI:
443 // Remove the interrupt that just completed from the local apic state.
444 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
445 updateISRV();
446 return;
447 case APIC_LOGICAL_DESTINATION:
448 newVal = val & 0xFF000000;
449 break;
450 case APIC_DESTINATION_FORMAT:
451 newVal = val | 0x0FFFFFFF;
452 break;
453 case APIC_SPURIOUS_INTERRUPT_VECTOR:
454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
455 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
456 if (val & (1 << 9))
457 warn("Focus processor checking not implemented.\n");
458 break;
459 case APIC_ERROR_STATUS:
460 {
461 if (regs[APIC_INTERNAL_STATE] & 0x1) {
462 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
463 newVal = 0;
464 } else {
465 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
466 return;
467 }
468
469 }
470 break;
471 case APIC_INTERRUPT_COMMAND_LOW:
472 {
473 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
474 // Check if we're already sending an IPI.
475 if (low.deliveryStatus) {
476 newVal = low;
477 break;
478 }
479 low = val;
480 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
481 TriggerIntMessage message = 0;
482 message.destination = high.destination;
483 message.vector = low.vector;
484 message.deliveryMode = low.deliveryMode;
485 message.destMode = low.destMode;
486 message.level = low.level;
487 message.trigger = low.trigger;
488 ApicList apics;
489 int numContexts = sys->numContexts();
490 switch (low.destShorthand) {
491 case 0:
492 if (message.deliveryMode == DeliveryMode::LowestPriority) {
493 panic("Lowest priority delivery mode "
494 "IPIs aren't implemented.\n");
495 }
496 if (message.destMode == 1) {
497 int dest = message.destination;
498 hack_once("Assuming logical destinations are 1 << id.\n");
499 for (int i = 0; i < numContexts; i++) {
500 if (dest & 0x1)
501 apics.push_back(i);
502 dest = dest >> 1;
503 }
504 } else {
505 if (message.destination == 0xFF) {
506 for (int i = 0; i < numContexts; i++) {
507 if (i == initialApicId) {
508 requestInterrupt(message.vector,
509 message.deliveryMode, message.trigger);
510 } else {
511 apics.push_back(i);
512 }
513 }
514 } else {
515 if (message.destination == initialApicId) {
516 requestInterrupt(message.vector,
517 message.deliveryMode, message.trigger);
518 } else {
519 apics.push_back(message.destination);
520 }
521 }
522 }
523 break;
524 case 1:
525 newVal = val;
526 requestInterrupt(message.vector,
527 message.deliveryMode, message.trigger);
528 break;
529 case 2:
530 requestInterrupt(message.vector,
531 message.deliveryMode, message.trigger);
532 // Fall through
533 case 3:
534 {
535 for (int i = 0; i < numContexts; i++) {
536 if (i != initialApicId) {
537 apics.push_back(i);
538 }
539 }
540 }
541 break;
542 }
543 // Record that an IPI is being sent if one actually is.
544 if (apics.size()) {
545 low.deliveryStatus = 1;
546 pendingIPIs += apics.size();
547 }
548 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
549 intMasterPort.sendMessage(apics, message, sys->isTimingMode());
550 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
551 }
552 break;
553 case APIC_LVT_TIMER:
554 case APIC_LVT_THERMAL_SENSOR:
555 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
556 case APIC_LVT_LINT0:
557 case APIC_LVT_LINT1:
558 case APIC_LVT_ERROR:
559 {
560 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
561 newVal = (val & ~readOnlyMask) |
562 (regs[reg] & readOnlyMask);
563 }
564 break;
565 case APIC_INITIAL_COUNT:
566 {
567 newVal = bits(val, 31, 0);
568 // Compute how many timer ticks we're being programmed for.
569 uint64_t newCount = newVal *
570 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
571 // Schedule on the edge of the next tick plus the new count.
572 Tick offset = curTick() % clockPeriod();
573 if (offset) {
574 reschedule(apicTimerEvent,
575 curTick() + (newCount + 1) *
576 clockPeriod() - offset, true);
577 } else {
578 if (newCount)
579 reschedule(apicTimerEvent,
580 curTick() + newCount *
581 clockPeriod(), true);
582 }
583 }
584 break;
585 case APIC_CURRENT_COUNT:
586 //Local APIC Current Count register is read only.
587 return;
588 case APIC_DIVIDE_CONFIGURATION:
589 newVal = val & 0xB;
590 break;
591 default:
592 break;
593 }
594 regs[reg] = newVal;
595 return;
596}
597
598
599X86ISA::Interrupts::Interrupts(Params * p)
600 : PioDevice(p), IntDevice(this, p->int_latency),
601 apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
602 pendingSmi(false), smiVector(0),
603 pendingNmi(false), nmiVector(0),
604 pendingExtInt(false), extIntVector(0),
605 pendingInit(false), initVector(0),
606 pendingStartup(false), startupVector(0),
607 startedUp(false), pendingUnmaskableInt(false),
608 pendingIPIs(0), cpu(NULL),
609 intSlavePort(name() + ".int_slave", this, this),
610 pioDelay(p->pio_latency)
611{
612 memset(regs, 0, sizeof(regs));
613 //Set the local apic DFR to the flat model.
614 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
615 ISRV = 0;
616 IRRV = 0;
617}
618
619
620bool
621X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
622{
623 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
624 if (pendingUnmaskableInt) {
625 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
626 return true;
627 }
628 if (rflags.intf) {
629 if (pendingExtInt) {
630 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
631 return true;
632 }
633 if (IRRV > ISRV && bits(IRRV, 7, 4) >
634 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
635 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
636 return true;
637 }
638 }
639 return false;
640}
641
642bool
643X86ISA::Interrupts::checkInterruptsRaw() const
644{
645 return pendingUnmaskableInt || pendingExtInt ||
646 (IRRV > ISRV && bits(IRRV, 7, 4) >
647 bits(regs[APIC_TASK_PRIORITY], 7, 4));
648}
649
650Fault
651X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
652{
653 assert(checkInterrupts(tc));
654 // These are all probably fairly uncommon, so we'll make them easier to
655 // check for.
656 if (pendingUnmaskableInt) {
657 if (pendingSmi) {
658 DPRINTF(LocalApic, "Generated SMI fault object.\n");
659 return std::make_shared<SystemManagementInterrupt>();
660 } else if (pendingNmi) {
661 DPRINTF(LocalApic, "Generated NMI fault object.\n");
662 return std::make_shared<NonMaskableInterrupt>(nmiVector);
663 } else if (pendingInit) {
664 DPRINTF(LocalApic, "Generated INIT fault object.\n");
665 return std::make_shared<InitInterrupt>(initVector);
666 } else if (pendingStartup) {
667 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
668 return std::make_shared<StartupInterrupt>(startupVector);
669 } else {
670 panic("pendingUnmaskableInt set, but no unmaskable "
671 "ints were pending.\n");
672 return NoFault;
673 }
674 } else if (pendingExtInt) {
675 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
676 return std::make_shared<ExternalInterrupt>(extIntVector);
677 } else {
678 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
679 // The only thing left are fixed and lowest priority interrupts.
680 return std::make_shared<ExternalInterrupt>(IRRV);
681 }
682}
683
684void
685X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
686{
687 assert(checkInterrupts(tc));
688 if (pendingUnmaskableInt) {
689 if (pendingSmi) {
690 DPRINTF(LocalApic, "SMI sent to core.\n");
691 pendingSmi = false;
692 } else if (pendingNmi) {
693 DPRINTF(LocalApic, "NMI sent to core.\n");
694 pendingNmi = false;
695 } else if (pendingInit) {
696 DPRINTF(LocalApic, "Init sent to core.\n");
697 pendingInit = false;
698 startedUp = false;
699 } else if (pendingStartup) {
700 DPRINTF(LocalApic, "SIPI sent to core.\n");
701 pendingStartup = false;
702 startedUp = true;
703 }
704 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
705 pendingUnmaskableInt = false;
706 } else if (pendingExtInt) {
707 pendingExtInt = false;
708 } else {
709 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
710 // Mark the interrupt as "in service".
711 ISRV = IRRV;
712 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
713 // Clear it out of the IRR.
714 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
715 updateIRRV();
716 }
717}
718
719void
720X86ISA::Interrupts::serialize(CheckpointOut &cp) const
721{
722 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
723 SERIALIZE_SCALAR(pendingSmi);
724 SERIALIZE_SCALAR(smiVector);
725 SERIALIZE_SCALAR(pendingNmi);
726 SERIALIZE_SCALAR(nmiVector);
727 SERIALIZE_SCALAR(pendingExtInt);
728 SERIALIZE_SCALAR(extIntVector);
729 SERIALIZE_SCALAR(pendingInit);
730 SERIALIZE_SCALAR(initVector);
731 SERIALIZE_SCALAR(pendingStartup);
732 SERIALIZE_SCALAR(startupVector);
733 SERIALIZE_SCALAR(startedUp);
734 SERIALIZE_SCALAR(pendingUnmaskableInt);
735 SERIALIZE_SCALAR(pendingIPIs);
736 SERIALIZE_SCALAR(IRRV);
737 SERIALIZE_SCALAR(ISRV);
738 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
739 SERIALIZE_SCALAR(apicTimerEventScheduled);
740 Tick apicTimerEventTick = apicTimerEvent.when();
741 SERIALIZE_SCALAR(apicTimerEventTick);
742}
743
744void
745X86ISA::Interrupts::unserialize(CheckpointIn &cp)
746{
747 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
748 UNSERIALIZE_SCALAR(pendingSmi);
749 UNSERIALIZE_SCALAR(smiVector);
750 UNSERIALIZE_SCALAR(pendingNmi);
751 UNSERIALIZE_SCALAR(nmiVector);
752 UNSERIALIZE_SCALAR(pendingExtInt);
753 UNSERIALIZE_SCALAR(extIntVector);
754 UNSERIALIZE_SCALAR(pendingInit);
755 UNSERIALIZE_SCALAR(initVector);
756 UNSERIALIZE_SCALAR(pendingStartup);
757 UNSERIALIZE_SCALAR(startupVector);
758 UNSERIALIZE_SCALAR(startedUp);
759 UNSERIALIZE_SCALAR(pendingUnmaskableInt);
760 UNSERIALIZE_SCALAR(pendingIPIs);
761 UNSERIALIZE_SCALAR(IRRV);
762 UNSERIALIZE_SCALAR(ISRV);
763 bool apicTimerEventScheduled;
764 UNSERIALIZE_SCALAR(apicTimerEventScheduled);
765 if (apicTimerEventScheduled) {
766 Tick apicTimerEventTick;
767 UNSERIALIZE_SCALAR(apicTimerEventTick);
768 if (apicTimerEvent.scheduled()) {
769 reschedule(apicTimerEvent, apicTimerEventTick, true);
770 } else {
771 schedule(apicTimerEvent, apicTimerEventTick);
772 }
773 }
774}
775
776X86ISA::Interrupts *
777X86LocalApicParams::create()
778{
779 return new X86ISA::Interrupts(this);
780}
781
782void
783X86ISA::Interrupts::processApicTimerEvent() {
784 if (triggerTimerInterrupt())
785 setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
786}
| 347}
348
349
350AddrRangeList
351X86ISA::Interrupts::getAddrRanges() const
352{
353 assert(cpu);
354 AddrRangeList ranges;
355 ranges.push_back(RangeSize(pioAddr, PageBytes));
356 return ranges;
357}
358
359
360AddrRangeList
361X86ISA::Interrupts::getIntAddrRange() const
362{
363 AddrRangeList ranges;
364 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
365 x86InterruptAddress(initialApicId, 0) +
366 PhysAddrAPICRangeSize));
367 return ranges;
368}
369
370
371uint32_t
372X86ISA::Interrupts::readReg(ApicRegIndex reg)
373{
374 if (reg >= APIC_TRIGGER_MODE(0) &&
375 reg <= APIC_TRIGGER_MODE(15)) {
376 panic("Local APIC Trigger Mode registers are unimplemented.\n");
377 }
378 switch (reg) {
379 case APIC_ARBITRATION_PRIORITY:
380 panic("Local APIC Arbitration Priority register unimplemented.\n");
381 break;
382 case APIC_PROCESSOR_PRIORITY:
383 panic("Local APIC Processor Priority register unimplemented.\n");
384 break;
385 case APIC_ERROR_STATUS:
386 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
387 break;
388 case APIC_CURRENT_COUNT:
389 {
390 if (apicTimerEvent.scheduled()) {
391 // Compute how many m5 ticks happen per count.
392 uint64_t ticksPerCount = clockPeriod() *
393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
394 // Compute how many m5 ticks are left.
395 uint64_t val = apicTimerEvent.when() - curTick();
396 // Turn that into a count.
397 val = (val + ticksPerCount - 1) / ticksPerCount;
398 return val;
399 } else {
400 return 0;
401 }
402 }
403 default:
404 break;
405 }
406 return regs[reg];
407}
408
409void
410X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
411{
412 uint32_t newVal = val;
413 if (reg >= APIC_IN_SERVICE(0) &&
414 reg <= APIC_IN_SERVICE(15)) {
415 panic("Local APIC In-Service registers are unimplemented.\n");
416 }
417 if (reg >= APIC_TRIGGER_MODE(0) &&
418 reg <= APIC_TRIGGER_MODE(15)) {
419 panic("Local APIC Trigger Mode registers are unimplemented.\n");
420 }
421 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
422 reg <= APIC_INTERRUPT_REQUEST(15)) {
423 panic("Local APIC Interrupt Request registers "
424 "are unimplemented.\n");
425 }
426 switch (reg) {
427 case APIC_ID:
428 newVal = val & 0xFF;
429 break;
430 case APIC_VERSION:
431 // The Local APIC Version register is read only.
432 return;
433 case APIC_TASK_PRIORITY:
434 newVal = val & 0xFF;
435 break;
436 case APIC_ARBITRATION_PRIORITY:
437 panic("Local APIC Arbitration Priority register unimplemented.\n");
438 break;
439 case APIC_PROCESSOR_PRIORITY:
440 panic("Local APIC Processor Priority register unimplemented.\n");
441 break;
442 case APIC_EOI:
443 // Remove the interrupt that just completed from the local apic state.
444 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
445 updateISRV();
446 return;
447 case APIC_LOGICAL_DESTINATION:
448 newVal = val & 0xFF000000;
449 break;
450 case APIC_DESTINATION_FORMAT:
451 newVal = val | 0x0FFFFFFF;
452 break;
453 case APIC_SPURIOUS_INTERRUPT_VECTOR:
454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
455 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
456 if (val & (1 << 9))
457 warn("Focus processor checking not implemented.\n");
458 break;
459 case APIC_ERROR_STATUS:
460 {
461 if (regs[APIC_INTERNAL_STATE] & 0x1) {
462 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
463 newVal = 0;
464 } else {
465 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
466 return;
467 }
468
469 }
470 break;
471 case APIC_INTERRUPT_COMMAND_LOW:
472 {
473 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
474 // Check if we're already sending an IPI.
475 if (low.deliveryStatus) {
476 newVal = low;
477 break;
478 }
479 low = val;
480 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
481 TriggerIntMessage message = 0;
482 message.destination = high.destination;
483 message.vector = low.vector;
484 message.deliveryMode = low.deliveryMode;
485 message.destMode = low.destMode;
486 message.level = low.level;
487 message.trigger = low.trigger;
488 ApicList apics;
489 int numContexts = sys->numContexts();
490 switch (low.destShorthand) {
491 case 0:
492 if (message.deliveryMode == DeliveryMode::LowestPriority) {
493 panic("Lowest priority delivery mode "
494 "IPIs aren't implemented.\n");
495 }
496 if (message.destMode == 1) {
497 int dest = message.destination;
498 hack_once("Assuming logical destinations are 1 << id.\n");
499 for (int i = 0; i < numContexts; i++) {
500 if (dest & 0x1)
501 apics.push_back(i);
502 dest = dest >> 1;
503 }
504 } else {
505 if (message.destination == 0xFF) {
506 for (int i = 0; i < numContexts; i++) {
507 if (i == initialApicId) {
508 requestInterrupt(message.vector,
509 message.deliveryMode, message.trigger);
510 } else {
511 apics.push_back(i);
512 }
513 }
514 } else {
515 if (message.destination == initialApicId) {
516 requestInterrupt(message.vector,
517 message.deliveryMode, message.trigger);
518 } else {
519 apics.push_back(message.destination);
520 }
521 }
522 }
523 break;
524 case 1:
525 newVal = val;
526 requestInterrupt(message.vector,
527 message.deliveryMode, message.trigger);
528 break;
529 case 2:
530 requestInterrupt(message.vector,
531 message.deliveryMode, message.trigger);
532 // Fall through
533 case 3:
534 {
535 for (int i = 0; i < numContexts; i++) {
536 if (i != initialApicId) {
537 apics.push_back(i);
538 }
539 }
540 }
541 break;
542 }
543 // Record that an IPI is being sent if one actually is.
544 if (apics.size()) {
545 low.deliveryStatus = 1;
546 pendingIPIs += apics.size();
547 }
548 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
549 intMasterPort.sendMessage(apics, message, sys->isTimingMode());
550 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
551 }
552 break;
553 case APIC_LVT_TIMER:
554 case APIC_LVT_THERMAL_SENSOR:
555 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
556 case APIC_LVT_LINT0:
557 case APIC_LVT_LINT1:
558 case APIC_LVT_ERROR:
559 {
560 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
561 newVal = (val & ~readOnlyMask) |
562 (regs[reg] & readOnlyMask);
563 }
564 break;
565 case APIC_INITIAL_COUNT:
566 {
567 newVal = bits(val, 31, 0);
568 // Compute how many timer ticks we're being programmed for.
569 uint64_t newCount = newVal *
570 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
571 // Schedule on the edge of the next tick plus the new count.
572 Tick offset = curTick() % clockPeriod();
573 if (offset) {
574 reschedule(apicTimerEvent,
575 curTick() + (newCount + 1) *
576 clockPeriod() - offset, true);
577 } else {
578 if (newCount)
579 reschedule(apicTimerEvent,
580 curTick() + newCount *
581 clockPeriod(), true);
582 }
583 }
584 break;
585 case APIC_CURRENT_COUNT:
586 //Local APIC Current Count register is read only.
587 return;
588 case APIC_DIVIDE_CONFIGURATION:
589 newVal = val & 0xB;
590 break;
591 default:
592 break;
593 }
594 regs[reg] = newVal;
595 return;
596}
597
598
599X86ISA::Interrupts::Interrupts(Params * p)
600 : PioDevice(p), IntDevice(this, p->int_latency),
601 apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
602 pendingSmi(false), smiVector(0),
603 pendingNmi(false), nmiVector(0),
604 pendingExtInt(false), extIntVector(0),
605 pendingInit(false), initVector(0),
606 pendingStartup(false), startupVector(0),
607 startedUp(false), pendingUnmaskableInt(false),
608 pendingIPIs(0), cpu(NULL),
609 intSlavePort(name() + ".int_slave", this, this),
610 pioDelay(p->pio_latency)
611{
612 memset(regs, 0, sizeof(regs));
613 //Set the local apic DFR to the flat model.
614 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
615 ISRV = 0;
616 IRRV = 0;
617}
618
619
620bool
621X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
622{
623 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
624 if (pendingUnmaskableInt) {
625 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
626 return true;
627 }
628 if (rflags.intf) {
629 if (pendingExtInt) {
630 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
631 return true;
632 }
633 if (IRRV > ISRV && bits(IRRV, 7, 4) >
634 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
635 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
636 return true;
637 }
638 }
639 return false;
640}
641
642bool
643X86ISA::Interrupts::checkInterruptsRaw() const
644{
645 return pendingUnmaskableInt || pendingExtInt ||
646 (IRRV > ISRV && bits(IRRV, 7, 4) >
647 bits(regs[APIC_TASK_PRIORITY], 7, 4));
648}
649
650Fault
651X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
652{
653 assert(checkInterrupts(tc));
654 // These are all probably fairly uncommon, so we'll make them easier to
655 // check for.
656 if (pendingUnmaskableInt) {
657 if (pendingSmi) {
658 DPRINTF(LocalApic, "Generated SMI fault object.\n");
659 return std::make_shared<SystemManagementInterrupt>();
660 } else if (pendingNmi) {
661 DPRINTF(LocalApic, "Generated NMI fault object.\n");
662 return std::make_shared<NonMaskableInterrupt>(nmiVector);
663 } else if (pendingInit) {
664 DPRINTF(LocalApic, "Generated INIT fault object.\n");
665 return std::make_shared<InitInterrupt>(initVector);
666 } else if (pendingStartup) {
667 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
668 return std::make_shared<StartupInterrupt>(startupVector);
669 } else {
670 panic("pendingUnmaskableInt set, but no unmaskable "
671 "ints were pending.\n");
672 return NoFault;
673 }
674 } else if (pendingExtInt) {
675 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
676 return std::make_shared<ExternalInterrupt>(extIntVector);
677 } else {
678 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
679 // The only thing left are fixed and lowest priority interrupts.
680 return std::make_shared<ExternalInterrupt>(IRRV);
681 }
682}
683
684void
685X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
686{
687 assert(checkInterrupts(tc));
688 if (pendingUnmaskableInt) {
689 if (pendingSmi) {
690 DPRINTF(LocalApic, "SMI sent to core.\n");
691 pendingSmi = false;
692 } else if (pendingNmi) {
693 DPRINTF(LocalApic, "NMI sent to core.\n");
694 pendingNmi = false;
695 } else if (pendingInit) {
696 DPRINTF(LocalApic, "Init sent to core.\n");
697 pendingInit = false;
698 startedUp = false;
699 } else if (pendingStartup) {
700 DPRINTF(LocalApic, "SIPI sent to core.\n");
701 pendingStartup = false;
702 startedUp = true;
703 }
704 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
705 pendingUnmaskableInt = false;
706 } else if (pendingExtInt) {
707 pendingExtInt = false;
708 } else {
709 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
710 // Mark the interrupt as "in service".
711 ISRV = IRRV;
712 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
713 // Clear it out of the IRR.
714 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
715 updateIRRV();
716 }
717}
718
719void
720X86ISA::Interrupts::serialize(CheckpointOut &cp) const
721{
722 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
723 SERIALIZE_SCALAR(pendingSmi);
724 SERIALIZE_SCALAR(smiVector);
725 SERIALIZE_SCALAR(pendingNmi);
726 SERIALIZE_SCALAR(nmiVector);
727 SERIALIZE_SCALAR(pendingExtInt);
728 SERIALIZE_SCALAR(extIntVector);
729 SERIALIZE_SCALAR(pendingInit);
730 SERIALIZE_SCALAR(initVector);
731 SERIALIZE_SCALAR(pendingStartup);
732 SERIALIZE_SCALAR(startupVector);
733 SERIALIZE_SCALAR(startedUp);
734 SERIALIZE_SCALAR(pendingUnmaskableInt);
735 SERIALIZE_SCALAR(pendingIPIs);
736 SERIALIZE_SCALAR(IRRV);
737 SERIALIZE_SCALAR(ISRV);
738 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
739 SERIALIZE_SCALAR(apicTimerEventScheduled);
740 Tick apicTimerEventTick = apicTimerEvent.when();
741 SERIALIZE_SCALAR(apicTimerEventTick);
742}
743
744void
745X86ISA::Interrupts::unserialize(CheckpointIn &cp)
746{
747 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
748 UNSERIALIZE_SCALAR(pendingSmi);
749 UNSERIALIZE_SCALAR(smiVector);
750 UNSERIALIZE_SCALAR(pendingNmi);
751 UNSERIALIZE_SCALAR(nmiVector);
752 UNSERIALIZE_SCALAR(pendingExtInt);
753 UNSERIALIZE_SCALAR(extIntVector);
754 UNSERIALIZE_SCALAR(pendingInit);
755 UNSERIALIZE_SCALAR(initVector);
756 UNSERIALIZE_SCALAR(pendingStartup);
757 UNSERIALIZE_SCALAR(startupVector);
758 UNSERIALIZE_SCALAR(startedUp);
759 UNSERIALIZE_SCALAR(pendingUnmaskableInt);
760 UNSERIALIZE_SCALAR(pendingIPIs);
761 UNSERIALIZE_SCALAR(IRRV);
762 UNSERIALIZE_SCALAR(ISRV);
763 bool apicTimerEventScheduled;
764 UNSERIALIZE_SCALAR(apicTimerEventScheduled);
765 if (apicTimerEventScheduled) {
766 Tick apicTimerEventTick;
767 UNSERIALIZE_SCALAR(apicTimerEventTick);
768 if (apicTimerEvent.scheduled()) {
769 reschedule(apicTimerEvent, apicTimerEventTick, true);
770 } else {
771 schedule(apicTimerEvent, apicTimerEventTick);
772 }
773 }
774}
775
776X86ISA::Interrupts *
777X86LocalApicParams::create()
778{
779 return new X86ISA::Interrupts(this);
780}
781
782void
783X86ISA::Interrupts::processApicTimerEvent() {
784 if (triggerTimerInterrupt())
785 setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
786}
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