1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/regs/apic.hh"
53#include "arch/x86/interrupts.hh"
54#include "arch/x86/intmessage.hh"
55#include "cpu/base.hh"
56#include "debug/LocalApic.hh"
57#include "dev/x86/i82094aa.hh"
58#include "dev/x86/pc.hh"
59#include "dev/x86/south_bridge.hh"
60#include "mem/packet_access.hh"
61#include "sim/system.hh"
62#include "sim/full_system.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71 shift = (shift + 1) % 8;
72 return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81 ApicRegIndex regNum;
82 paddr &= ~mask(3);
83 switch (paddr)
84 {
85 case 0x20:
86 regNum = APIC_ID;
87 break;
88 case 0x30:
89 regNum = APIC_VERSION;
90 break;
91 case 0x80:
92 regNum = APIC_TASK_PRIORITY;
93 break;
94 case 0x90:
95 regNum = APIC_ARBITRATION_PRIORITY;
96 break;
97 case 0xA0:
98 regNum = APIC_PROCESSOR_PRIORITY;
99 break;
100 case 0xB0:
101 regNum = APIC_EOI;
102 break;
103 case 0xD0:
104 regNum = APIC_LOGICAL_DESTINATION;
105 break;
106 case 0xE0:
107 regNum = APIC_DESTINATION_FORMAT;
108 break;
109 case 0xF0:
110 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111 break;
112 case 0x100:
113 case 0x108:
114 case 0x110:
115 case 0x118:
116 case 0x120:
117 case 0x128:
118 case 0x130:
119 case 0x138:
120 case 0x140:
121 case 0x148:
122 case 0x150:
123 case 0x158:
124 case 0x160:
125 case 0x168:
126 case 0x170:
127 case 0x178:
128 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129 break;
130 case 0x180:
131 case 0x188:
132 case 0x190:
133 case 0x198:
134 case 0x1A0:
135 case 0x1A8:
136 case 0x1B0:
137 case 0x1B8:
138 case 0x1C0:
139 case 0x1C8:
140 case 0x1D0:
141 case 0x1D8:
142 case 0x1E0:
143 case 0x1E8:
144 case 0x1F0:
145 case 0x1F8:
146 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147 break;
148 case 0x200:
149 case 0x208:
150 case 0x210:
151 case 0x218:
152 case 0x220:
153 case 0x228:
154 case 0x230:
155 case 0x238:
156 case 0x240:
157 case 0x248:
158 case 0x250:
159 case 0x258:
160 case 0x260:
161 case 0x268:
162 case 0x270:
163 case 0x278:
164 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165 break;
166 case 0x280:
167 regNum = APIC_ERROR_STATUS;
168 break;
169 case 0x300:
170 regNum = APIC_INTERRUPT_COMMAND_LOW;
171 break;
172 case 0x310:
173 regNum = APIC_INTERRUPT_COMMAND_HIGH;
174 break;
175 case 0x320:
176 regNum = APIC_LVT_TIMER;
177 break;
178 case 0x330:
179 regNum = APIC_LVT_THERMAL_SENSOR;
180 break;
181 case 0x340:
182 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183 break;
184 case 0x350:
185 regNum = APIC_LVT_LINT0;
186 break;
187 case 0x360:
188 regNum = APIC_LVT_LINT1;
189 break;
190 case 0x370:
191 regNum = APIC_LVT_ERROR;
192 break;
193 case 0x380:
194 regNum = APIC_INITIAL_COUNT;
195 break;
196 case 0x390:
197 regNum = APIC_CURRENT_COUNT;
198 break;
199 case 0x3E0:
200 regNum = APIC_DIVIDE_CONFIGURATION;
201 break;
202 default:
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr);
205 break;
206 }
207 return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214 Addr offset = pkt->getAddr() - pioAddr;
215 //Make sure we're at least only accessing one register.
216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg = decodeAddr(offset);
219 uint32_t val = htog(readReg(reg));
220 DPRINTF(LocalApic,
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
222 reg, offset, val);
223 pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224 pkt->makeAtomicResponse();
225 return latency;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231 Addr offset = pkt->getAddr() - pioAddr;
232 //Make sure we're at least only accessing one register.
233 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg = decodeAddr(offset);
236 uint32_t val = regs[reg];
237 pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238 DPRINTF(LocalApic,
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg, offset, gtoh(val));
241 setReg(reg, gtoh(val));
242 pkt->makeAtomicResponse();
243 return latency;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247 uint8_t deliveryMode, bool level)
248{
249 /*
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.
252 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
253 */
254 if (deliveryMode == DeliveryMode::Fixed ||
255 deliveryMode == DeliveryMode::LowestPriority) {
256 DPRINTF(LocalApic, "Interrupt is an %s.\n",
257 DeliveryMode::names[deliveryMode]);
258 // Queue up the interrupt in the IRR.
259 if (vector > IRRV)
260 IRRV = vector;
261 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
262 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
263 if (level) {
264 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265 } else {
266 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
267 }
268 }
269 } else if (!DeliveryMode::isReserved(deliveryMode)) {
270 DPRINTF(LocalApic, "Interrupt is an %s.\n",
271 DeliveryMode::names[deliveryMode]);
272 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
273 pendingUnmaskableInt = pendingSmi = true;
274 smiVector = vector;
275 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
276 pendingUnmaskableInt = pendingNmi = true;
277 nmiVector = vector;
278 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
279 pendingExtInt = true;
280 extIntVector = vector;
281 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
282 pendingUnmaskableInt = pendingInit = true;
283 initVector = vector;
284 } else if (deliveryMode == DeliveryMode::SIPI &&
285 !pendingStartup && !startedUp) {
286 pendingUnmaskableInt = pendingStartup = true;
287 startupVector = vector;
288 }
289 }
290 if (FullSystem)
291 cpu->wakeup();
292}
293
294
295void
296X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
297{
298 assert(newCPU);
299 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
300 panic("Local APICs can't be moved between CPUs"
301 " with different IDs.\n");
302 }
303 cpu = newCPU;
304 initialApicId = cpu->cpuId();
305 regs[APIC_ID] = (initialApicId << 24);
306 pioAddr = x86LocalAPICAddress(initialApicId, 0);
307}
308
309
310void
311X86ISA::Interrupts::init()
312{
313 //
314 // The local apic must register its address ranges on both its pio port
315 // via the basicpiodevice(piodevice) init() function and its int port
316 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
317 //
318 BasicPioDevice::init();
319 IntDev::init();
320
321 // the slave port has a range so inform the connected master
322 intSlavePort.sendRangeChange();
323}
324
325
326Tick
327X86ISA::Interrupts::recvMessage(PacketPtr pkt)
328{
329 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
330 assert(pkt->cmd == MemCmd::MessageReq);
331 switch(offset)
332 {
333 case 0:
334 {
335 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
336 DPRINTF(LocalApic,
337 "Got Trigger Interrupt message with vector %#x.\n",
338 message.vector);
339
340 requestInterrupt(message.vector,
341 message.deliveryMode, message.trigger);
342 }
343 break;
344 default:
345 panic("Local apic got unknown interrupt message at offset %#x.\n",
346 offset);
347 break;
348 }
349 pkt->makeAtomicResponse();
350 return latency;
351}
352
353
354Tick
355X86ISA::Interrupts::recvResponse(PacketPtr pkt)
356{
357 assert(!pkt->isError());
358 assert(pkt->cmd == MemCmd::MessageResp);
359 if (--pendingIPIs == 0) {
360 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
361 // Record that the ICR is now idle.
362 low.deliveryStatus = 0;
363 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
364 }
365 DPRINTF(LocalApic, "ICR is now idle.\n");
366 return 0;
367}
368
369
370AddrRangeList
371X86ISA::Interrupts::getAddrRanges() const
372{
373 AddrRangeList ranges;
374 AddrRange range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
375 x86LocalAPICAddress(initialApicId, 0) +
376 PageBytes);
377 ranges.push_back(range);
378 return ranges;
379}
380
381
382AddrRangeList
383X86ISA::Interrupts::getIntAddrRange() const
384{
385 AddrRangeList ranges;
386 ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
387 x86InterruptAddress(initialApicId, 0) +
388 PhysAddrAPICRangeSize));
389 return ranges;
390}
391
392
393uint32_t
394X86ISA::Interrupts::readReg(ApicRegIndex reg)
395{
396 if (reg >= APIC_TRIGGER_MODE(0) &&
397 reg <= APIC_TRIGGER_MODE(15)) {
398 panic("Local APIC Trigger Mode registers are unimplemented.\n");
399 }
400 switch (reg) {
401 case APIC_ARBITRATION_PRIORITY:
402 panic("Local APIC Arbitration Priority register unimplemented.\n");
403 break;
404 case APIC_PROCESSOR_PRIORITY:
405 panic("Local APIC Processor Priority register unimplemented.\n");
406 break;
407 case APIC_ERROR_STATUS:
408 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
409 break;
410 case APIC_CURRENT_COUNT:
411 {
412 if (apicTimerEvent.scheduled()) {
413 assert(clock);
414 // Compute how many m5 ticks happen per count.
415 uint64_t ticksPerCount = clock *
416 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
417 // Compute how many m5 ticks are left.
418 uint64_t val = apicTimerEvent.when() - curTick();
419 // Turn that into a count.
420 val = (val + ticksPerCount - 1) / ticksPerCount;
421 return val;
422 } else {
423 return 0;
424 }
425 }
426 default:
427 break;
428 }
429 return regs[reg];
430}
431
432void
433X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
434{
435 uint32_t newVal = val;
436 if (reg >= APIC_IN_SERVICE(0) &&
437 reg <= APIC_IN_SERVICE(15)) {
438 panic("Local APIC In-Service registers are unimplemented.\n");
439 }
440 if (reg >= APIC_TRIGGER_MODE(0) &&
441 reg <= APIC_TRIGGER_MODE(15)) {
442 panic("Local APIC Trigger Mode registers are unimplemented.\n");
443 }
444 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
445 reg <= APIC_INTERRUPT_REQUEST(15)) {
446 panic("Local APIC Interrupt Request registers "
447 "are unimplemented.\n");
448 }
449 switch (reg) {
450 case APIC_ID:
451 newVal = val & 0xFF;
452 break;
453 case APIC_VERSION:
454 // The Local APIC Version register is read only.
455 return;
456 case APIC_TASK_PRIORITY:
457 newVal = val & 0xFF;
458 break;
459 case APIC_ARBITRATION_PRIORITY:
460 panic("Local APIC Arbitration Priority register unimplemented.\n");
461 break;
462 case APIC_PROCESSOR_PRIORITY:
463 panic("Local APIC Processor Priority register unimplemented.\n");
464 break;
465 case APIC_EOI:
466 // Remove the interrupt that just completed from the local apic state.
467 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
468 updateISRV();
469 return;
470 case APIC_LOGICAL_DESTINATION:
471 newVal = val & 0xFF000000;
472 break;
473 case APIC_DESTINATION_FORMAT:
474 newVal = val | 0x0FFFFFFF;
475 break;
476 case APIC_SPURIOUS_INTERRUPT_VECTOR:
477 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
478 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
479 if (val & (1 << 9))
480 warn("Focus processor checking not implemented.\n");
481 break;
482 case APIC_ERROR_STATUS:
483 {
484 if (regs[APIC_INTERNAL_STATE] & 0x1) {
485 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
486 newVal = 0;
487 } else {
488 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
489 return;
490 }
491
492 }
493 break;
494 case APIC_INTERRUPT_COMMAND_LOW:
495 {
496 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
497 // Check if we're already sending an IPI.
498 if (low.deliveryStatus) {
499 newVal = low;
500 break;
501 }
502 low = val;
503 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
504 // Record that an IPI is being sent.
505 low.deliveryStatus = 1;
506 TriggerIntMessage message = 0;
507 message.destination = high.destination;
508 message.vector = low.vector;
509 message.deliveryMode = low.deliveryMode;
510 message.destMode = low.destMode;
511 message.level = low.level;
512 message.trigger = low.trigger;
513 bool timing(sys->isTimingMode());
514 // Be careful no updates of the delivery status bit get lost.
515 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
516 ApicList apics;
517 int numContexts = sys->numContexts();
518 switch (low.destShorthand) {
519 case 0:
520 if (message.deliveryMode == DeliveryMode::LowestPriority) {
521 panic("Lowest priority delivery mode "
522 "IPIs aren't implemented.\n");
523 }
524 if (message.destMode == 1) {
525 int dest = message.destination;
526 hack_once("Assuming logical destinations are 1 << id.\n");
527 for (int i = 0; i < numContexts; i++) {
528 if (dest & 0x1)
529 apics.push_back(i);
530 dest = dest >> 1;
531 }
532 } else {
533 if (message.destination == 0xFF) {
534 for (int i = 0; i < numContexts; i++) {
535 if (i == initialApicId) {
536 requestInterrupt(message.vector,
537 message.deliveryMode, message.trigger);
538 } else {
539 apics.push_back(i);
540 }
541 }
542 } else {
543 if (message.destination == initialApicId) {
544 requestInterrupt(message.vector,
545 message.deliveryMode, message.trigger);
546 } else {
547 apics.push_back(message.destination);
548 }
549 }
550 }
551 break;
552 case 1:
553 newVal = val;
554 requestInterrupt(message.vector,
555 message.deliveryMode, message.trigger);
556 break;
557 case 2:
558 requestInterrupt(message.vector,
559 message.deliveryMode, message.trigger);
560 // Fall through
561 case 3:
562 {
563 for (int i = 0; i < numContexts; i++) {
564 if (i != initialApicId) {
565 apics.push_back(i);
566 }
567 }
568 }
569 break;
570 }
571 pendingIPIs += apics.size();
572 intMasterPort.sendMessage(apics, message, timing);
573 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
574 }
575 break;
576 case APIC_LVT_TIMER:
577 case APIC_LVT_THERMAL_SENSOR:
578 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
579 case APIC_LVT_LINT0:
580 case APIC_LVT_LINT1:
581 case APIC_LVT_ERROR:
582 {
583 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
584 newVal = (val & ~readOnlyMask) |
585 (regs[reg] & readOnlyMask);
586 }
587 break;
588 case APIC_INITIAL_COUNT:
589 {
590 assert(clock);
591 newVal = bits(val, 31, 0);
592 // Compute how many timer ticks we're being programmed for.
593 uint64_t newCount = newVal *
594 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
595 // Schedule on the edge of the next tick plus the new count.
596 Tick offset = curTick() % clock;
597 if (offset) {
598 reschedule(apicTimerEvent,
599 curTick() + (newCount + 1) * clock - offset, true);
600 } else {
601 reschedule(apicTimerEvent,
602 curTick() + newCount * clock, true);
603 }
604 }
605 break;
606 case APIC_CURRENT_COUNT:
607 //Local APIC Current Count register is read only.
608 return;
609 case APIC_DIVIDE_CONFIGURATION:
610 newVal = val & 0xB;
611 break;
612 default:
613 break;
614 }
615 regs[reg] = newVal;
616 return;
617}
618
619
620X86ISA::Interrupts::Interrupts(Params * p) :
621 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
622 apicTimerEvent(this),
623 pendingSmi(false), smiVector(0),
624 pendingNmi(false), nmiVector(0),
625 pendingExtInt(false), extIntVector(0),
626 pendingInit(false), initVector(0),
627 pendingStartup(false), startupVector(0),
628 startedUp(false), pendingUnmaskableInt(false),
629 pendingIPIs(0), cpu(NULL),
630 intSlavePort(name() + ".int_slave", this, this, latency)
631{
632 // Override the default clock
633 clock = 0;
634 pioSize = PageBytes;
635 memset(regs, 0, sizeof(regs));
636 //Set the local apic DFR to the flat model.
637 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
638 ISRV = 0;
639 IRRV = 0;
640}
641
642
643bool
644X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
645{
646 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
647 if (pendingUnmaskableInt) {
648 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
649 return true;
650 }
651 if (rflags.intf) {
652 if (pendingExtInt) {
653 DPRINTF(LocalApic, "Reported pending external interrupt.\n");
654 return true;
655 }
656 if (IRRV > ISRV && bits(IRRV, 7, 4) >
657 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
658 DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
659 return true;
660 }
661 }
662 return false;
663}
664
665Fault
666X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
667{
668 assert(checkInterrupts(tc));
669 // These are all probably fairly uncommon, so we'll make them easier to
670 // check for.
671 if (pendingUnmaskableInt) {
672 if (pendingSmi) {
673 DPRINTF(LocalApic, "Generated SMI fault object.\n");
674 return new SystemManagementInterrupt();
675 } else if (pendingNmi) {
676 DPRINTF(LocalApic, "Generated NMI fault object.\n");
677 return new NonMaskableInterrupt(nmiVector);
678 } else if (pendingInit) {
679 DPRINTF(LocalApic, "Generated INIT fault object.\n");
680 return new InitInterrupt(initVector);
681 } else if (pendingStartup) {
682 DPRINTF(LocalApic, "Generating SIPI fault object.\n");
683 return new StartupInterrupt(startupVector);
684 } else {
685 panic("pendingUnmaskableInt set, but no unmaskable "
686 "ints were pending.\n");
687 return NoFault;
688 }
689 } else if (pendingExtInt) {
690 DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
691 return new ExternalInterrupt(extIntVector);
692 } else {
693 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
694 // The only thing left are fixed and lowest priority interrupts.
695 return new ExternalInterrupt(IRRV);
696 }
697}
698
699void
700X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
701{
702 assert(checkInterrupts(tc));
703 if (pendingUnmaskableInt) {
704 if (pendingSmi) {
705 DPRINTF(LocalApic, "SMI sent to core.\n");
706 pendingSmi = false;
707 } else if (pendingNmi) {
708 DPRINTF(LocalApic, "NMI sent to core.\n");
709 pendingNmi = false;
710 } else if (pendingInit) {
711 DPRINTF(LocalApic, "Init sent to core.\n");
712 pendingInit = false;
713 startedUp = false;
714 } else if (pendingStartup) {
715 DPRINTF(LocalApic, "SIPI sent to core.\n");
716 pendingStartup = false;
717 startedUp = true;
718 }
719 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
720 pendingUnmaskableInt = false;
721 } else if (pendingExtInt) {
722 pendingExtInt = false;
723 } else {
724 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
725 // Mark the interrupt as "in service".
726 ISRV = IRRV;
727 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
728 // Clear it out of the IRR.
729 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
730 updateIRRV();
731 }
732}
733
734void
735X86ISA::Interrupts::serialize(std::ostream &os)
736{
737 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
738 SERIALIZE_SCALAR(clock);
739 SERIALIZE_SCALAR(pendingSmi);
740 SERIALIZE_SCALAR(smiVector);
741 SERIALIZE_SCALAR(pendingNmi);
742 SERIALIZE_SCALAR(nmiVector);
743 SERIALIZE_SCALAR(pendingExtInt);
744 SERIALIZE_SCALAR(extIntVector);
745 SERIALIZE_SCALAR(pendingInit);
746 SERIALIZE_SCALAR(initVector);
747 SERIALIZE_SCALAR(pendingStartup);
748 SERIALIZE_SCALAR(startupVector);
749 SERIALIZE_SCALAR(startedUp);
750 SERIALIZE_SCALAR(pendingUnmaskableInt);
751 SERIALIZE_SCALAR(pendingIPIs);
752 SERIALIZE_SCALAR(IRRV);
753 SERIALIZE_SCALAR(ISRV);
754 bool apicTimerEventScheduled = apicTimerEvent.scheduled();
755 SERIALIZE_SCALAR(apicTimerEventScheduled);
756 Tick apicTimerEventTick = apicTimerEvent.when();
757 SERIALIZE_SCALAR(apicTimerEventTick);
758}
759
760void
761X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
762{
763 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
764 UNSERIALIZE_SCALAR(clock);
765 UNSERIALIZE_SCALAR(pendingSmi);
766 UNSERIALIZE_SCALAR(smiVector);
767 UNSERIALIZE_SCALAR(pendingNmi);
768 UNSERIALIZE_SCALAR(nmiVector);
769 UNSERIALIZE_SCALAR(pendingExtInt);
770 UNSERIALIZE_SCALAR(extIntVector);
771 UNSERIALIZE_SCALAR(pendingInit);
772 UNSERIALIZE_SCALAR(initVector);
773 UNSERIALIZE_SCALAR(pendingStartup);
774 UNSERIALIZE_SCALAR(startupVector);
775 UNSERIALIZE_SCALAR(startedUp);
776 UNSERIALIZE_SCALAR(pendingUnmaskableInt);
777 UNSERIALIZE_SCALAR(pendingIPIs);
778 UNSERIALIZE_SCALAR(IRRV);
779 UNSERIALIZE_SCALAR(ISRV);
780 bool apicTimerEventScheduled;
781 UNSERIALIZE_SCALAR(apicTimerEventScheduled);
782 if (apicTimerEventScheduled) {
783 Tick apicTimerEventTick;
784 UNSERIALIZE_SCALAR(apicTimerEventTick);
785 if (apicTimerEvent.scheduled()) {
786 reschedule(apicTimerEvent, apicTimerEventTick, true);
787 } else {
788 schedule(apicTimerEvent, apicTimerEventTick);
789 }
790 }
791}
792
793X86ISA::Interrupts *
794X86LocalApicParams::create()
795{
796 return new X86ISA::Interrupts(this);
797}