1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/interrupts.hh"
59#include "cpu/base.hh"
60
61int divideFromConf(uint32_t conf)
62{
63 // This figures out what division we want from the division configuration
64 // register in the local APIC. The encoding is a little odd but it can
65 // be deciphered fairly easily.
66 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
67 shift = (shift + 1) % 8;
68 return 1 << shift;
69}
70
71uint32_t
72X86ISA::Interrupts::readRegNoEffect(ApicRegIndex reg)
73{
74 return regs[reg];
75}
76
77uint32_t
78X86ISA::Interrupts::readReg(ApicRegIndex reg, ThreadContext * tc)
79{
80 if (reg >= APIC_TRIGGER_MODE(0) &&
81 reg <= APIC_TRIGGER_MODE(15)) {
82 panic("Local APIC Trigger Mode registers are unimplemented.\n");
83 }
84 switch (reg) {
85 case APIC_ARBITRATION_PRIORITY:
86 panic("Local APIC Arbitration Priority register unimplemented.\n");
87 break;
88 case APIC_PROCESSOR_PRIORITY:
89 panic("Local APIC Processor Priority register unimplemented.\n");
90 break;
91 case APIC_EOI:
92 panic("Local APIC EOI register unimplemented.\n");
93 break;
94 case APIC_ERROR_STATUS:
95 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
96 break;
97 case APIC_INTERRUPT_COMMAND_LOW:
98 panic("Local APIC Interrupt Command low"
99 " register unimplemented.\n");
100 break;
101 case APIC_INTERRUPT_COMMAND_HIGH:
102 panic("Local APIC Interrupt Command high"
103 " register unimplemented.\n");
104 break;
105 case APIC_CURRENT_COUNT:
106 {
107 uint32_t val = regs[reg] - tc->getCpuPtr()->curCycle();
108 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
109 return val;
110 }
111 default:
112 break;
113 }
114 return readRegNoEffect(reg);
115}
116
117void
118X86ISA::Interrupts::setRegNoEffect(ApicRegIndex reg, uint32_t val)
119{
120 regs[reg] = val;
121}
122
123void
124X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val, ThreadContext *tc)
125{
126 uint32_t newVal = val;
127 if (reg >= APIC_IN_SERVICE(0) &&
128 reg <= APIC_IN_SERVICE(15)) {
129 panic("Local APIC In-Service registers are unimplemented.\n");
130 }
131 if (reg >= APIC_TRIGGER_MODE(0) &&
132 reg <= APIC_TRIGGER_MODE(15)) {
133 panic("Local APIC Trigger Mode registers are unimplemented.\n");
134 }
135 if (reg >= APIC_INTERRUPT_REQUEST(0) &&
136 reg <= APIC_INTERRUPT_REQUEST(15)) {
137 panic("Local APIC Interrupt Request registers "
138 "are unimplemented.\n");
139 }
140 switch (reg) {
141 case APIC_ID:
142 newVal = val & 0xFF;
143 break;
144 case APIC_VERSION:
145 // The Local APIC Version register is read only.
146 return;
147 case APIC_TASK_PRIORITY:
148 newVal = val & 0xFF;
149 break;
150 case APIC_ARBITRATION_PRIORITY:
151 panic("Local APIC Arbitration Priority register unimplemented.\n");
152 break;
153 case APIC_PROCESSOR_PRIORITY:
154 panic("Local APIC Processor Priority register unimplemented.\n");
155 break;
156 case APIC_EOI:
157 panic("Local APIC EOI register unimplemented.\n");
158 break;
159 case APIC_LOGICAL_DESTINATION:
160 newVal = val & 0xFF000000;
161 break;
162 case APIC_DESTINATION_FORMAT:
163 newVal = val | 0x0FFFFFFF;
164 break;
165 case APIC_SPURIOUS_INTERRUPT_VECTOR:
166 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
167 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
168 if (val & (1 << 9))
169 warn("Focus processor checking not implemented.\n");
170 break;
171 case APIC_ERROR_STATUS:
172 {
173 if (regs[APIC_INTERNAL_STATE] & 0x1) {
174 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
175 newVal = 0;
176 } else {
177 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
178 return;
179 }
180
181 }
182 break;
183 case APIC_INTERRUPT_COMMAND_LOW:
184 panic("Local APIC Interrupt Command low"
185 " register unimplemented.\n");
186 break;
187 case APIC_INTERRUPT_COMMAND_HIGH:
188 panic("Local APIC Interrupt Command high"
189 " register unimplemented.\n");
190 break;
191 case APIC_LVT_TIMER:
192 case APIC_LVT_THERMAL_SENSOR:
193 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
194 case APIC_LVT_LINT0:
195 case APIC_LVT_LINT1:
196 case APIC_LVT_ERROR:
197 {
198 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
199 newVal = (val & ~readOnlyMask) |
200 (regs[reg] & readOnlyMask);
201 }
202 break;
203 case APIC_INITIAL_COUNT:
204 newVal = bits(val, 31, 0);
205 regs[APIC_CURRENT_COUNT] =
206 tc->getCpuPtr()->curCycle() +
207 (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])) * newVal;
208 //FIXME This should schedule the timer event.
209 break;
210 case APIC_CURRENT_COUNT:
211 //Local APIC Current Count register is read only.
212 return;
213 case APIC_DIVIDE_CONFIGURATION:
214 newVal = val & 0xB;
215 break;
216 default:
217 break;
218 }
219 setRegNoEffect(reg, newVal);
220 return;
221}
222
223X86ISA::Interrupts *
224X86LocalApicParams::create()
225{
226 return new X86ISA::Interrupts(this);
227}