1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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254 TriggerIntMessage message = pkt->get<TriggerIntMessage>();
255 uint8_t vector = message.vector;
256 DPRINTF(LocalApic,
257 "Got Trigger Interrupt message with vector %#x.\n",
258 vector);
259 // Make sure we're really supposed to get this.
260 assert((message.destMode == 0 && message.destination == id) ||
261 (bits((int)message.destination, id)));
262 if (DeliveryMode::isUnmaskable(message.deliveryMode)) {
263 DPRINTF(LocalApic, "Interrupt is an %s and unmaskable.\n",
264 DeliveryMode::names[message.deliveryMode]);
265 panic("Unmaskable interrupts aren't implemented.\n");
266 } else if (DeliveryMode::isMaskable(message.deliveryMode)) {
267 DPRINTF(LocalApic, "Interrupt is an %s and maskable.\n",
268 DeliveryMode::names[message.deliveryMode]);
269 // Queue up the interrupt in the IRR.
270 if (vector > IRRV)
271 IRRV = vector;
272 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
273 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
274 if (message.trigger) {
275 // Level triggered.
276 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
277 } else {
278 // Edge triggered.
279 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
280 }
281 }
282 }
283 }
284 break;
285 default:
286 panic("Local apic got unknown interrupt message at offset %#x.\n",
287 offset);
288 break;
289 }
290 delete pkt->req;

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446 regs[reg] = newVal;
447 return;
448}
449
450bool
451X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const
452{
453 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
454 if (IRRV > ISRV && rflags.intf &&
455 bits(IRRV, 7, 4) > bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
456 return true;
457 }
458 return false;
459}
460
461Fault
462X86ISA::Interrupts::getInterrupt(ThreadContext * tc)
463{
464 assert(check_interrupts(tc));
465 return new ExternalInterrupt(IRRV);
466}
467
468void
469X86ISA::Interrupts::updateIntrInfo(ThreadContext * tc)
470{
471 assert(check_interrupts(tc));
472 // Mark the interrupt as "in service".
473 ISRV = IRRV;
474 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
475 // Clear it out of the IRR.
476 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
477 updateIRRV();
478}
479
480X86ISA::Interrupts *
481X86LocalApicParams::create()
482{
483 return new X86ISA::Interrupts(this);
484}