1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/interrupts.hh"
59#include "cpu/base.hh"
60
61int divideFromConf(uint32_t conf)
62{
63 // This figures out what division we want from the division configuration
64 // register in the local APIC. The encoding is a little odd but it can
65 // be deciphered fairly easily.
66 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
67 shift = (shift + 1) % 8;
68 return 1 << shift;
69}
70
71uint32_t
72X86ISA::Interrupts::readRegNoEffect(ApicRegIndex reg)
73{
74 return regs[reg];
75}
76
77uint32_t
78X86ISA::Interrupts::readReg(ApicRegIndex reg, ThreadContext * tc)
79{
80 if (reg >= APIC_TRIGGER_MODE(0) &&
81 reg <= APIC_TRIGGER_MODE(15)) {
82 panic("Local APIC Trigger Mode registers are unimplemented.\n");
83 }
84 switch (reg) {
85 case APIC_ARBITRATION_PRIORITY:
86 panic("Local APIC Arbitration Priority register unimplemented.\n");

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99 " register unimplemented.\n");
100 break;
101 case APIC_INTERRUPT_COMMAND_HIGH:
102 panic("Local APIC Interrupt Command high"
103 " register unimplemented.\n");
104 break;
105 case APIC_CURRENT_COUNT:
106 {
107 uint32_t val = regs[reg] - tc->getCpuPtr()->curCycle();
108 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
109 return val;
110 }
111 default:
112 break;
113 }
114 return readRegNoEffect(reg);
115}
116
117void
118X86ISA::Interrupts::setRegNoEffect(ApicRegIndex reg, uint32_t val)
119{
120 regs[reg] = val;
121}
122
123void
124X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val, ThreadContext *tc)
125{
126 uint32_t newVal = val;
127 if (reg >= APIC_IN_SERVICE(0) &&
128 reg <= APIC_IN_SERVICE(15)) {
129 panic("Local APIC In-Service registers are unimplemented.\n");
130 }
131 if (reg >= APIC_TRIGGER_MODE(0) &&
132 reg <= APIC_TRIGGER_MODE(15)) {
133 panic("Local APIC Trigger Mode registers are unimplemented.\n");

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196 case APIC_LVT_ERROR:
197 {
198 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
199 newVal = (val & ~readOnlyMask) |
200 (regs[reg] & readOnlyMask);
201 }
202 break;
203 case APIC_INITIAL_COUNT:
204 newVal = bits(val, 31, 0);
205 regs[APIC_CURRENT_COUNT] =
206 tc->getCpuPtr()->curCycle() +
207 (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])) * newVal;
208 //FIXME This should schedule the timer event.
209 break;
210 case APIC_CURRENT_COUNT:
211 //Local APIC Current Count register is read only.
212 return;
213 case APIC_DIVIDE_CONFIGURATION:
214 newVal = val & 0xB;
215 break;
216 default:
217 break;
218 }
219 setRegNoEffect(reg, newVal);
220 return;
221}
222
223X86ISA::Interrupts *
224X86LocalApicParams::create()
225{
226 return new X86ISA::Interrupts(this);
227}