faults.cc (9765:da0e0df0ba97) faults.cc (10100:24cfe67c0749)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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240 tc->pcState(pc);
241
242 tc->setMiscReg(MISCREG_TSG_BASE, 0);
243 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
244
245 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
246 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
247
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 231 unchanged lines hidden (view full) ---

240 tc->pcState(pc);
241
242 tc->setMiscReg(MISCREG_TSG_BASE, 0);
243 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
244
245 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
246 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
247
248 SegAttr tslAttr = 0;
249 tslAttr.present = 1;
250 tslAttr.type = 2; // LDT
248 tc->setMiscReg(MISCREG_TSL, 0);
249 tc->setMiscReg(MISCREG_TSL_BASE, 0);
250 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
251 tc->setMiscReg(MISCREG_TSL, 0);
252 tc->setMiscReg(MISCREG_TSL_BASE, 0);
253 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
251 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
254 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
252
255
256 SegAttr trAttr = 0;
257 trAttr.present = 1;
258 trAttr.type = 3; // Busy 16-bit TSS
253 tc->setMiscReg(MISCREG_TR, 0);
254 tc->setMiscReg(MISCREG_TR_BASE, 0);
255 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
259 tc->setMiscReg(MISCREG_TR, 0);
260 tc->setMiscReg(MISCREG_TR_BASE, 0);
261 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
256 tc->setMiscReg(MISCREG_TR_ATTR, 0);
262 tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
257
258 // This value should be the family/model/stepping of the processor.
259 // (page 418). It should be consistent with the value from CPUID, but
260 // the actual value probably doesn't matter much.
261 tc->setIntReg(INTREG_RDX, 0);
262
263 tc->setMiscReg(MISCREG_DR0, 0);
264 tc->setMiscReg(MISCREG_DR1, 0);

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264 // This value should be the family/model/stepping of the processor.
265 // (page 418). It should be consistent with the value from CPUID, but
266 // the actual value probably doesn't matter much.
267 tc->setIntReg(INTREG_RDX, 0);
268
269 tc->setMiscReg(MISCREG_DR0, 0);
270 tc->setMiscReg(MISCREG_DR1, 0);

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