faults.cc (8740:253aeee61e66) faults.cc (8806:669e93d79ed9)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
54 {
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 38 unchanged lines hidden (view full) ---

47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
54 {
55 if (FullSystem) {
56 PCState pcState = tc->pcState();
57 Addr pc = pcState.pc();
58 DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
59 pc, vector, describe());
60 using namespace X86ISAInst::RomLabels;
61 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
62 MicroPC entry;
63 if (m5reg.mode == LongMode) {
64 if (isSoft()) {
65 entry = extern_label_longModeSoftInterrupt;
66 } else {
67 entry = extern_label_longModeInterrupt;
68 }
55 if (!FullSystem) {
56 FaultBase::invoke(tc, inst);
57 return;
58 }
59
60 PCState pcState = tc->pcState();
61 Addr pc = pcState.pc();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
63 pc, vector, describe());
64 using namespace X86ISAInst::RomLabels;
65 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
66 MicroPC entry;
67 if (m5reg.mode == LongMode) {
68 if (isSoft()) {
69 entry = extern_label_longModeSoftInterrupt;
69 } else {
70 } else {
70 entry = extern_label_legacyModeInterrupt;
71 entry = extern_label_longModeInterrupt;
71 }
72 }
72 tc->setIntReg(INTREG_MICRO(1), vector);
73 tc->setIntReg(INTREG_MICRO(7), pc);
74 if (errorCode != (uint64_t)(-1)) {
75 if (m5reg.mode == LongMode) {
76 entry = extern_label_longModeInterruptWithError;
77 } else {
78 panic("Legacy mode interrupts with error codes "
79 "aren't implementde.\n");
80 }
81 // Software interrupts shouldn't have error codes. If one
82 // does, there would need to be microcode to set it up.
83 assert(!isSoft());
84 tc->setIntReg(INTREG_MICRO(15), errorCode);
85 }
86 pcState.upc(romMicroPC(entry));
87 pcState.nupc(romMicroPC(entry) + 1);
88 tc->pcState(pcState);
89 } else {
73 } else {
90 FaultBase::invoke(tc, inst);
74 entry = extern_label_legacyModeInterrupt;
91 }
75 }
76 tc->setIntReg(INTREG_MICRO(1), vector);
77 tc->setIntReg(INTREG_MICRO(7), pc);
78 if (errorCode != (uint64_t)(-1)) {
79 if (m5reg.mode == LongMode) {
80 entry = extern_label_longModeInterruptWithError;
81 } else {
82 panic("Legacy mode interrupts with error codes "
83 "aren't implementde.\n");
84 }
85 // Software interrupts shouldn't have error codes. If one
86 // does, there would need to be microcode to set it up.
87 assert(!isSoft());
88 tc->setIntReg(INTREG_MICRO(15), errorCode);
89 }
90 pcState.upc(romMicroPC(entry));
91 pcState.nupc(romMicroPC(entry) + 1);
92 tc->pcState(pcState);
92 }
93
94 std::string
95 X86FaultBase::describe() const
96 {
97 std::stringstream ss;
98 ccprintf(ss, "%s", mnemonic());
99 if (errorCode != (uint64_t)(-1)) {
100 ccprintf(ss, "(%#x)", errorCode);
101 }
102
103 return ss.str();
104 }
105
106 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
107 {
108 X86FaultBase::invoke(tc);
93 }
94
95 std::string
96 X86FaultBase::describe() const
97 {
98 std::stringstream ss;
99 ccprintf(ss, "%s", mnemonic());
100 if (errorCode != (uint64_t)(-1)) {
101 ccprintf(ss, "(%#x)", errorCode);
102 }
103
104 return ss.str();
105 }
106
107 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
108 {
109 X86FaultBase::invoke(tc);
109 if (FullSystem) {
110 // This is the same as a fault, but it happens -after- the
111 // instruction.
112 PCState pc = tc->pcState();
113 pc.uEnd();
114 }
110 if (!FullSystem)
111 return;
112
113 // This is the same as a fault, but it happens -after- the
114 // instruction.
115 PCState pc = tc->pcState();
116 pc.uEnd();
115 }
116
117 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
118 {
119 panic("Abort exception!");
120 }
121
122 void

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118
119 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
120 {
121 panic("Abort exception!");
122 }
123
124 void

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