faults.cc (7681:61e31534522d) faults.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
59 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
60 {
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
59 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
60 {
61 Addr pc = tc->readPC();
61 PCState pcState = tc->pcState();
62 Addr pc = pcState.pc();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
63 using namespace X86ISAInst::RomLabels;
64 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
65 MicroPC entry;
66 if (m5reg.mode == LongMode) {
67 if (isSoft()) {
68 entry = extern_label_longModeSoftInterrupt;
69 } else {

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81 panic("Legacy mode interrupts with error codes "
82 "aren't implementde.\n");
83 }
84 // Software interrupts shouldn't have error codes. If one does,
85 // there would need to be microcode to set it up.
86 assert(!isSoft());
87 tc->setIntReg(INTREG_MICRO(15), errorCode);
88 }
63 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
64 using namespace X86ISAInst::RomLabels;
65 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
66 MicroPC entry;
67 if (m5reg.mode == LongMode) {
68 if (isSoft()) {
69 entry = extern_label_longModeSoftInterrupt;
70 } else {

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82 panic("Legacy mode interrupts with error codes "
83 "aren't implementde.\n");
84 }
85 // Software interrupts shouldn't have error codes. If one does,
86 // there would need to be microcode to set it up.
87 assert(!isSoft());
88 tc->setIntReg(INTREG_MICRO(15), errorCode);
89 }
89 tc->setMicroPC(romMicroPC(entry));
90 tc->setNextMicroPC(romMicroPC(entry) + 1);
90 pcState.upc(romMicroPC(entry));
91 pcState.nupc(romMicroPC(entry) + 1);
92 tc->pcState(pcState);
91 }
92
93 std::string
94 X86FaultBase::describe() const
95 {
96 std::stringstream ss;
97 ccprintf(ss, "%s", mnemonic());
98 if (errorCode != (uint64_t)(-1)) {
99 ccprintf(ss, "(%#x)", errorCode);
100 }
101
102 return ss.str();
103 }
104
105 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
106 {
107 X86FaultBase::invoke(tc);
108 // This is the same as a fault, but it happens -after- the instruction.
93 }
94
95 std::string
96 X86FaultBase::describe() const
97 {
98 std::stringstream ss;
99 ccprintf(ss, "%s", mnemonic());
100 if (errorCode != (uint64_t)(-1)) {
101 ccprintf(ss, "(%#x)", errorCode);
102 }
103
104 return ss.str();
105 }
106
107 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
108 {
109 X86FaultBase::invoke(tc);
110 // This is the same as a fault, but it happens -after- the instruction.
109 tc->setPC(tc->readNextPC());
110 tc->setNextPC(tc->readNextNPC());
111 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
111 PCState pc = tc->pcState();
112 pc.uEnd();
112 }
113
114 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
115 {
116 panic("Abort exception!");
117 }
118
119 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)

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202 tc->setMiscReg(MISCREG_CS_BASE,
203 0x00000000ffff0000ULL);
204 tc->setMiscReg(MISCREG_CS_EFF_BASE,
205 0x00000000ffff0000ULL);
206 // This has the base value pre-added.
207 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
208 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
209
113 }
114
115 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
116 {
117 panic("Abort exception!");
118 }
119
120 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)

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203 tc->setMiscReg(MISCREG_CS_BASE,
204 0x00000000ffff0000ULL);
205 tc->setMiscReg(MISCREG_CS_EFF_BASE,
206 0x00000000ffff0000ULL);
207 // This has the base value pre-added.
208 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
209 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
210
210 tc->setPC(0x000000000000fff0ULL +
211 tc->readMiscReg(MISCREG_CS_BASE));
212 tc->setNextPC(tc->readPC() + sizeof(MachInst));
211 PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
212 tc->pcState(pc);
213
214 tc->setMiscReg(MISCREG_TSG_BASE, 0);
215 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
216
217 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
218 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
219
220 tc->setMiscReg(MISCREG_TSL, 0);

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238 tc->setMiscReg(MISCREG_DR3, 0);
239
240 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
241 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
242
243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
213
214 tc->setMiscReg(MISCREG_TSG_BASE, 0);
215 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
216
217 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
218 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
219
220 tc->setMiscReg(MISCREG_TSL, 0);

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238 tc->setMiscReg(MISCREG_DR3, 0);
239
240 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
241 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
242
243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246 tc->setMicroPC(romMicroPC(entry));
247 tc->setNextMicroPC(romMicroPC(entry) + 1);
246 pc.upc(romMicroPC(entry));
247 pc.nupc(romMicroPC(entry) + 1);
248 tc->pcState(pc);
248 }
249
250 void
251 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
252 {
253 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
254 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
255 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
258 }
259
260 tc->setMiscReg(MISCREG_CS, vector << 8);
261 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
262 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
263 // This has the base value pre-added.
264 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
265
249 }
250
251 void
252 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
253 {
254 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
255 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
256 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
257 panic("Startup IPI recived outside of real mode. "
258 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
259 }
260
261 tc->setMiscReg(MISCREG_CS, vector << 8);
262 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
263 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
264 // This has the base value pre-added.
265 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
266
266 tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
267 tc->setNextPC(tc->readPC() + sizeof(MachInst));
267 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
268 }
269
270#else
271
272 void
273 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
274 {
275 panic("Unrecognized/invalid instruction executed:\n %s",

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269
270#else
271
272 void
273 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
274 {
275 panic("Unrecognized/invalid instruction executed:\n %s",

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