faults.cc (7625:b1e69203bae9) faults.cc (7678:f19b6a3a8cec)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51#include "sim/process.hh"
52#else
53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51#include "sim/process.hh"
52#else
53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
59 void X86FaultBase::invoke(ThreadContext * tc)
59 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
60 {
61 Addr pc = tc->readPC();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
63 using namespace X86ISAInst::RomLabels;
64 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
65 MicroPC entry;
66 if (m5reg.mode == LongMode) {
67 if (isSoft()) {

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97 ccprintf(ss, "%s", mnemonic());
98 if (errorCode != (uint64_t)(-1)) {
99 ccprintf(ss, "(%#x)", errorCode);
100 }
101
102 return ss.str();
103 }
104
60 {
61 Addr pc = tc->readPC();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
63 using namespace X86ISAInst::RomLabels;
64 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
65 MicroPC entry;
66 if (m5reg.mode == LongMode) {
67 if (isSoft()) {

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97 ccprintf(ss, "%s", mnemonic());
98 if (errorCode != (uint64_t)(-1)) {
99 ccprintf(ss, "(%#x)", errorCode);
100 }
101
102 return ss.str();
103 }
104
105 void X86Trap::invoke(ThreadContext * tc)
105 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
106 {
107 X86FaultBase::invoke(tc);
108 // This is the same as a fault, but it happens -after- the instruction.
109 tc->setPC(tc->readNextPC());
110 tc->setNextPC(tc->readNextNPC());
111 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
112 }
113
106 {
107 X86FaultBase::invoke(tc);
108 // This is the same as a fault, but it happens -after- the instruction.
109 tc->setPC(tc->readNextPC());
110 tc->setNextPC(tc->readNextNPC());
111 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
112 }
113
114 void X86Abort::invoke(ThreadContext * tc)
114 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
115 {
116 panic("Abort exception!");
117 }
118
115 {
116 panic("Abort exception!");
117 }
118
119 void PageFault::invoke(ThreadContext * tc)
119 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
120 {
121 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
122 X86FaultBase::invoke(tc);
123 /*
124 * If something bad happens while trying to enter the page fault
125 * handler, I'm pretty sure that's a double fault and then all bets are
126 * off. That means it should be safe to update this state now.
127 */

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136 PageFault::describe() const
137 {
138 std::stringstream ss;
139 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
140 return ss.str();
141 }
142
143 void
120 {
121 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
122 X86FaultBase::invoke(tc);
123 /*
124 * If something bad happens while trying to enter the page fault
125 * handler, I'm pretty sure that's a double fault and then all bets are
126 * off. That means it should be safe to update this state now.
127 */

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136 PageFault::describe() const
137 {
138 std::stringstream ss;
139 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
140 return ss.str();
141 }
142
143 void
144 InitInterrupt::invoke(ThreadContext *tc)
144 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
145 {
146 DPRINTF(Faults, "Init interrupt.\n");
147 // The otherwise unmodified integer registers should be set to 0.
148 for (int index = 0; index < NUM_INTREGS; index++) {
149 tc->setIntReg(index, 0);
150 }
151
152 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);

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243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246 tc->setMicroPC(romMicroPC(entry));
247 tc->setNextMicroPC(romMicroPC(entry) + 1);
248 }
249
250 void
145 {
146 DPRINTF(Faults, "Init interrupt.\n");
147 // The otherwise unmodified integer registers should be set to 0.
148 for (int index = 0; index < NUM_INTREGS; index++) {
149 tc->setIntReg(index, 0);
150 }
151
152 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);

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243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246 tc->setMicroPC(romMicroPC(entry));
247 tc->setNextMicroPC(romMicroPC(entry) + 1);
248 }
249
250 void
251 StartupInterrupt::invoke(ThreadContext *tc)
251 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
252 {
253 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
254 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
255 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
258 }
259

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265
266 tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
267 tc->setNextPC(tc->readPC() + sizeof(MachInst));
268 }
269
270#else
271
272 void
252 {
253 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
254 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
255 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
258 }
259

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265
266 tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
267 tc->setNextPC(tc->readPC() + sizeof(MachInst));
268 }
269
270#else
271
272 void
273 PageFault::invoke(ThreadContext * tc)
273 PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
274 {
275 PageFaultErrorCode code = errorCode;
276 const char *modeStr = "";
277 if (code.fetch)
278 modeStr = "execute";
279 else if (code.write)
280 modeStr = "write";
281 else
282 modeStr = "read";
283 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
284 }
285
286#endif
287} // namespace X86ISA
288
274 {
275 PageFaultErrorCode code = errorCode;
276 const char *modeStr = "";
277 if (code.fetch)
278 modeStr = "execute";
279 else if (code.write)
280 modeStr = "write";
281 else
282 modeStr = "read";
283 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
284 }
285
286#endif
287} // namespace X86ISA
288