faults.cc (5909:ecbd27e5d1f8) | faults.cc (6048:65a321a3a691) |
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1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 171 unchanged lines hidden (view full) --- 180 std::string 181 PageFault::describe() const 182 { 183 std::stringstream ss; 184 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); 185 return ss.str(); 186 } 187 | 1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 171 unchanged lines hidden (view full) --- 180 std::string 181 PageFault::describe() const 182 { 183 std::stringstream ss; 184 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); 185 return ss.str(); 186 } 187 |
188 void 189 InitInterrupt::invoke(ThreadContext *tc) 190 { 191 DPRINTF(Faults, "Init interrupt.\n"); 192 // The otherwise unmodified integer registers should be set to 0. 193 for (int index = 0; index < NUM_INTREGS; index++) { 194 tc->setIntReg(index, 0); 195 } 196 197 CR0 cr0 = tc->readMiscReg(MISCREG_CR0); 198 CR0 newCR0 = 1 << 4; 199 newCR0.cd = cr0.cd; 200 newCR0.nw = cr0.nw; 201 tc->setMiscReg(MISCREG_CR0, newCR0); 202 tc->setMiscReg(MISCREG_CR2, 0); 203 tc->setMiscReg(MISCREG_CR3, 0); 204 tc->setMiscReg(MISCREG_CR4, 0); 205 206 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL); 207 208 tc->setMiscReg(MISCREG_EFER, 0); 209 210 SegAttr dataAttr = 0; 211 dataAttr.writable = 1; 212 dataAttr.readable = 1; 213 dataAttr.expandDown = 0; 214 dataAttr.dpl = 0; 215 dataAttr.defaultSize = 0; 216 217 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 218 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 219 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 220 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0); 221 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 222 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); 223 } 224 225 SegAttr codeAttr = 0; 226 codeAttr.writable = 0; 227 codeAttr.readable = 1; 228 codeAttr.expandDown = 0; 229 codeAttr.dpl = 0; 230 codeAttr.defaultSize = 0; 231 232 tc->setMiscReg(MISCREG_CS, 0xf000); 233 tc->setMiscReg(MISCREG_CS_BASE, 234 0x00000000ffff0000ULL); 235 tc->setMiscReg(MISCREG_CS_EFF_BASE, 236 0x00000000ffff0000ULL); 237 // This has the base value pre-added. 238 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 239 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); 240 241 tc->setPC(0x000000000000fff0ULL + 242 tc->readMiscReg(MISCREG_CS_BASE)); 243 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 244 245 tc->setMiscReg(MISCREG_TSG_BASE, 0); 246 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 247 248 tc->setMiscReg(MISCREG_IDTR_BASE, 0); 249 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 250 251 tc->setMiscReg(MISCREG_TSL, 0); 252 tc->setMiscReg(MISCREG_TSL_BASE, 0); 253 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff); 254 tc->setMiscReg(MISCREG_TSL_ATTR, 0); 255 256 tc->setMiscReg(MISCREG_TR, 0); 257 tc->setMiscReg(MISCREG_TR_BASE, 0); 258 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 259 tc->setMiscReg(MISCREG_TR_ATTR, 0); 260 261 // This value should be the family/model/stepping of the processor. 262 // (page 418). It should be consistent with the value from CPUID, but 263 // the actual value probably doesn't matter much. 264 tc->setIntReg(INTREG_RDX, 0); 265 266 tc->setMiscReg(MISCREG_DR0, 0); 267 tc->setMiscReg(MISCREG_DR1, 0); 268 tc->setMiscReg(MISCREG_DR2, 0); 269 tc->setMiscReg(MISCREG_DR3, 0); 270 271 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL); 272 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL); 273 274 // We're now in real mode, effectively at CPL 0 275 HandyM5Reg m5Reg = 0; 276 m5Reg.mode = LegacyMode; 277 m5Reg.submode = RealMode; 278 m5Reg.cpl = 0; 279 tc->setMiscReg(MISCREG_M5_REG, m5Reg); 280 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt; 281 tc->setMicroPC(romMicroPC(entry)); 282 tc->setNextMicroPC(romMicroPC(entry) + 1); 283 } 284 |
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188#endif 189} // namespace X86ISA 190 | 285#endif 286} // namespace X86ISA 287 |