faults.cc (5895:569e3b31a868) | faults.cc (5909:ecbd27e5d1f8) |
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1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 89 unchanged lines hidden (view full) --- 98#include "arch/x86/tlb.hh" 99#endif 100 101namespace X86ISA 102{ 103#if FULL_SYSTEM 104 void X86FaultBase::invoke(ThreadContext * tc) 105 { | 1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 89 unchanged lines hidden (view full) --- 98#include "arch/x86/tlb.hh" 99#endif 100 101namespace X86ISA 102{ 103#if FULL_SYSTEM 104 void X86FaultBase::invoke(ThreadContext * tc) 105 { |
106 Addr pc = tc->readPC(); 107 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe()); |
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106 using namespace X86ISAInst::RomLabels; 107 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 108 MicroPC entry; 109 if (m5reg.mode == LongMode) { 110 if (isSoft()) { 111 entry = extern_label_longModeSoftInterrupt; 112 } else { 113 entry = extern_label_longModeInterrupt; 114 } 115 } else { 116 entry = extern_label_legacyModeInterrupt; 117 } 118 tc->setIntReg(INTREG_MICRO(1), vector); | 108 using namespace X86ISAInst::RomLabels; 109 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 110 MicroPC entry; 111 if (m5reg.mode == LongMode) { 112 if (isSoft()) { 113 entry = extern_label_longModeSoftInterrupt; 114 } else { 115 entry = extern_label_longModeInterrupt; 116 } 117 } else { 118 entry = extern_label_legacyModeInterrupt; 119 } 120 tc->setIntReg(INTREG_MICRO(1), vector); |
119 tc->setIntReg(INTREG_MICRO(7), tc->readPC()); | 121 tc->setIntReg(INTREG_MICRO(7), pc); |
120 if (errorCode != (uint64_t)(-1)) { 121 if (m5reg.mode == LongMode) { 122 entry = extern_label_longModeInterruptWithError; 123 } else { 124 panic("Legacy mode interrupts with error codes " 125 "aren't implementde.\n"); 126 } 127 // Software interrupts shouldn't have error codes. If one does, 128 // there would need to be microcode to set it up. 129 assert(!isSoft()); 130 tc->setIntReg(INTREG_MICRO(15), errorCode); 131 } 132 tc->setMicroPC(romMicroPC(entry)); 133 tc->setNextMicroPC(romMicroPC(entry) + 1); 134 } | 122 if (errorCode != (uint64_t)(-1)) { 123 if (m5reg.mode == LongMode) { 124 entry = extern_label_longModeInterruptWithError; 125 } else { 126 panic("Legacy mode interrupts with error codes " 127 "aren't implementde.\n"); 128 } 129 // Software interrupts shouldn't have error codes. If one does, 130 // there would need to be microcode to set it up. 131 assert(!isSoft()); 132 tc->setIntReg(INTREG_MICRO(15), errorCode); 133 } 134 tc->setMicroPC(romMicroPC(entry)); 135 tc->setNextMicroPC(romMicroPC(entry) + 1); 136 } |
137 138 std::string 139 X86FaultBase::describe() const 140 { 141 std::stringstream ss; 142 ccprintf(ss, "%s", mnemonic()); 143 if (errorCode != (uint64_t)(-1)) { 144 ccprintf(ss, "(%#x)", errorCode); 145 } 146 147 return ss.str(); 148 } |
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135 136 void X86Trap::invoke(ThreadContext * tc) 137 { 138 X86FaultBase::invoke(tc); 139 // This is the same as a fault, but it happens -after- the instruction. 140 tc->setPC(tc->readNextPC()); 141 tc->setNextPC(tc->readNextNPC()); 142 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); --- 15 unchanged lines hidden (view full) --- 158 */ 159 if (m5reg.mode == LongMode) { 160 tc->setMiscReg(MISCREG_CR2, addr); 161 } else { 162 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 163 } 164 } 165 | 149 150 void X86Trap::invoke(ThreadContext * tc) 151 { 152 X86FaultBase::invoke(tc); 153 // This is the same as a fault, but it happens -after- the instruction. 154 tc->setPC(tc->readNextPC()); 155 tc->setNextPC(tc->readNextNPC()); 156 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); --- 15 unchanged lines hidden (view full) --- 172 */ 173 if (m5reg.mode == LongMode) { 174 tc->setMiscReg(MISCREG_CR2, addr); 175 } else { 176 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 177 } 178 } 179 |
180 std::string 181 PageFault::describe() const 182 { 183 std::stringstream ss; 184 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); 185 return ss.str(); 186 } 187 |
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166#endif 167} // namespace X86ISA 168 | 188#endif 189} // namespace X86ISA 190 |