faults.cc (5881:73c0aaaaf186) | faults.cc (5895:569e3b31a868) |
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1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 149 unchanged lines hidden (view full) --- 158 */ 159 if (m5reg.mode == LongMode) { 160 tc->setMiscReg(MISCREG_CR2, addr); 161 } else { 162 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 163 } 164 } 165 | 1/* 2 * Copyright (c) 2003-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 149 unchanged lines hidden (view full) --- 158 */ 159 if (m5reg.mode == LongMode) { 160 tc->setMiscReg(MISCREG_CR2, addr); 161 } else { 162 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 163 } 164 } 165 |
166 void FakeITLBFault::invoke(ThreadContext * tc) 167 { 168 // Start the page table walker. 169 tc->getITBPtr()->walk(tc, vaddr, write, execute); 170 } 171 172 void FakeDTLBFault::invoke(ThreadContext * tc) 173 { 174 // Start the page table walker. 175 tc->getDTBPtr()->walk(tc, vaddr, write, execute); 176 } 177 178#else // !FULL_SYSTEM 179 void FakeITLBFault::invoke(ThreadContext * tc) 180 { 181 DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n", 182 vaddr, tc->readPC()); 183 Process *p = tc->getProcessPtr(); 184 TlbEntry entry; 185 bool success = p->pTable->lookup(vaddr, entry); 186 if(!success) { 187 panic("Tried to execute unmapped address %#x.\n", vaddr); 188 } else { 189 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 190 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 191 entry.pageStart()); 192 tc->getITBPtr()->insert(alignedVaddr, entry); 193 } 194 } 195 196 void FakeDTLBFault::invoke(ThreadContext * tc) 197 { 198 DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n", 199 vaddr, tc->readPC()); 200 Process *p = tc->getProcessPtr(); 201 TlbEntry entry; 202 bool success = p->pTable->lookup(vaddr, entry); 203 if(!success) { 204 p->checkAndAllocNextPage(vaddr); 205 success = p->pTable->lookup(vaddr, entry); 206 } 207 if(!success) { 208 panic("Tried to access unmapped address %#x.\n", vaddr); 209 } else { 210 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 211 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 212 entry.pageStart()); 213 tc->getDTBPtr()->insert(alignedVaddr, entry); 214 } 215 } | |
216#endif 217} // namespace X86ISA 218 | 166#endif 167} // namespace X86ISA 168 |