faults.cc (5857:8cd8e1393990) faults.cc (5858:54f64fb1bd62)
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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96#include "sim/process.hh"
97#else
98#include "arch/x86/tlb.hh"
99#endif
100
101namespace X86ISA
102{
103#if FULL_SYSTEM
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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96#include "sim/process.hh"
97#else
98#include "arch/x86/tlb.hh"
99#endif
100
101namespace X86ISA
102{
103#if FULL_SYSTEM
104 void X86Trap::invoke(ThreadContext * tc)
104 void X86FaultBase::invoke(ThreadContext * tc)
105 {
105 {
106 panic("X86 faults are not implemented!");
107 }
108
109 void X86Abort::invoke(ThreadContext * tc)
110 {
111 panic("X86 faults are not implemented!");
112 }
113
114 void X86Interrupt::invoke(ThreadContext * tc)
115 {
116 using namespace X86ISAInst::RomLabels;
117 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
118 MicroPC entry;
119 if (m5reg.mode == LongMode) {
106 using namespace X86ISAInst::RomLabels;
107 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
108 MicroPC entry;
109 if (m5reg.mode == LongMode) {
120 entry = extern_label_longModeInterrupt;
110 if (isSoft()) {
111 entry = extern_label_longModeSoftInterrupt;
112 } else {
113 entry = extern_label_longModeInterrupt;
114 }
121 } else {
122 entry = extern_label_legacyModeInterrupt;
123 }
124 tc->setIntReg(INTREG_MICRO(1), vector);
125 tc->setIntReg(INTREG_MICRO(7), tc->readPC());
126 if (errorCode != (uint64_t)(-1)) {
115 } else {
116 entry = extern_label_legacyModeInterrupt;
117 }
118 tc->setIntReg(INTREG_MICRO(1), vector);
119 tc->setIntReg(INTREG_MICRO(7), tc->readPC());
120 if (errorCode != (uint64_t)(-1)) {
121 if (m5reg.mode == LongMode) {
122 entry = extern_label_longModeInterruptWithError;
123 } else {
124 panic("Legacy mode interrupts with error codes "
125 "aren't implementde.\n");
126 }
127 // Software interrupts shouldn't have error codes. If one does,
128 // there would need to be microcode to set it up.
129 assert(!isSoft());
127 tc->setIntReg(INTREG_MICRO(15), errorCode);
128 }
129 tc->setMicroPC(romMicroPC(entry));
130 tc->setNextMicroPC(romMicroPC(entry) + 1);
131 }
130 tc->setIntReg(INTREG_MICRO(15), errorCode);
131 }
132 tc->setMicroPC(romMicroPC(entry));
133 tc->setNextMicroPC(romMicroPC(entry) + 1);
134 }
135
136 void X86Trap::invoke(ThreadContext * tc)
137 {
138 X86FaultBase::invoke(tc);
139 // This is the same as a fault, but it happens -after- the instruction.
140 tc->setPC(tc->readNextPC());
141 tc->setNextPC(tc->readNextNPC());
142 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
143 }
132
144
145 void X86Abort::invoke(ThreadContext * tc)
146 {
147 panic("Abort exception!");
148 }
149
150 void PageFault::invoke(ThreadContext * tc)
151 {
152 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
153 X86FaultBase::invoke(tc);
154 /*
155 * If something bad happens while trying to enter the page fault
156 * handler, I'm pretty sure that's a double fault and then all bets are
157 * off. That means it should be safe to update this state now.
158 */
159 if (m5reg.mode == LongMode) {
160 tc->setMiscReg(MISCREG_CR2, addr);
161 } else {
162 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
163 }
164 }
165
133 void FakeITLBFault::invoke(ThreadContext * tc)
134 {
135 // Start the page table walker.
136 tc->getITBPtr()->walk(tc, vaddr);
137 }
138
139 void FakeDTLBFault::invoke(ThreadContext * tc)
140 {

--- 45 unchanged lines hidden --- 		166 void FakeITLBFault::invoke(ThreadContext * tc)
167 {
168 // Start the page table walker.
169 tc->getITBPtr()->walk(tc, vaddr);
170 }
171
172 void FakeDTLBFault::invoke(ThreadContext * tc)
173 {

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