faults.cc (5245:d94bb8af9f76) faults.cc (5681:54c2d92f601e)
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 71 unchanged lines hidden (view full) ---

80 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
81 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
82 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 *
85 * Authors: Gabe Black
86 */
87
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 71 unchanged lines hidden (view full) ---

80 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
81 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
82 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 *
85 * Authors: Gabe Black
86 */
87
88#include "arch/x86/decoder.hh"
88#include "arch/x86/faults.hh"
89#include "base/trace.hh"
90#include "config/full_system.hh"
91#include "cpu/thread_context.hh"
92#if !FULL_SYSTEM
93#include "arch/x86/isa_traits.hh"
94#include "mem/page_table.hh"
95#include "sim/process.hh"

--- 11 unchanged lines hidden (view full) ---

107
108 void X86Abort::invoke(ThreadContext * tc)
109 {
110 panic("X86 faults are not implemented!");
111 }
112
113 void X86Interrupt::invoke(ThreadContext * tc)
114 {
89#include "arch/x86/faults.hh"
90#include "base/trace.hh"
91#include "config/full_system.hh"
92#include "cpu/thread_context.hh"
93#if !FULL_SYSTEM
94#include "arch/x86/isa_traits.hh"
95#include "mem/page_table.hh"
96#include "sim/process.hh"

--- 11 unchanged lines hidden (view full) ---

108
109 void X86Abort::invoke(ThreadContext * tc)
110 {
111 panic("X86 faults are not implemented!");
112 }
113
114 void X86Interrupt::invoke(ThreadContext * tc)
115 {
115 panic("X86 faults are not implemented!");
116 using namespace X86ISAInst::RomLabels;
117 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
118 MicroPC entry;
119 if (m5reg.mode == LongMode) {
120 entry = extern_label_longModeInterrupt;
121 } else {
122 entry = extern_label_legacyModeInterrupt;
123 }
124 tc->setIntReg(INTREG_MICRO(1), vector);
125 tc->setIntReg(INTREG_MICRO(7), tc->readPC());
126 tc->setMicroPC(romMicroPC(entry));
127 tc->setNextMicroPC(romMicroPC(entry) + 1);
116 }
117
118 void FakeITLBFault::invoke(ThreadContext * tc)
119 {
120 // Start the page table walker.
121 tc->getITBPtr()->walk(tc, vaddr);
122 }
123

--- 47 unchanged lines hidden --- 		128 }
129
130 void FakeITLBFault::invoke(ThreadContext * tc)
131 {
132 // Start the page table walker.
133 tc->getITBPtr()->walk(tc, vaddr);
134 }
135

--- 47 unchanged lines hidden ---