faults.cc (5130:2b64ee899f60) faults.cc (5184:8782de2949e5)
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 104 unchanged lines hidden (view full) ---

113 panic("X86 faults are not implemented!");
114 }
115#else // !FULL_SYSTEM
116 void FakeITLBFault::invoke(ThreadContext * tc)
117 {
118 DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
119 vaddr, tc->readPC());
120 Process *p = tc->getProcessPtr();
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 104 unchanged lines hidden (view full) ---

113 panic("X86 faults are not implemented!");
114 }
115#else // !FULL_SYSTEM
116 void FakeITLBFault::invoke(ThreadContext * tc)
117 {
118 DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
119 vaddr, tc->readPC());
120 Process *p = tc->getProcessPtr();
121 Addr paddr;
122 bool success = p->pTable->translate(vaddr, paddr);
121 TlbEntry entry;
122 bool success = p->pTable->lookup(vaddr, entry);
123 if(!success) {
124 panic("Tried to execute unmapped address %#x.\n", vaddr);
125 } else {
123 if(!success) {
124 panic("Tried to execute unmapped address %#x.\n", vaddr);
125 } else {
126 TlbEntry entry;
127 entry.pageStart = p->pTable->pageAlign(paddr);
128 entry.writeable = false;
129 entry.user = true;
130 entry.uncacheable = false;
131 entry.global = false;
132 entry.patBit = 0;
133 entry.noExec = false;
134 entry.size = PageBytes;
135 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
136 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
137 tc->getITBPtr()->insert(alignedVaddr, entry);
138 }
139 }
140
141 void FakeDTLBFault::invoke(ThreadContext * tc)
142 {
143 DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
144 vaddr, tc->readPC());
145 Process *p = tc->getProcessPtr();
126 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
127 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
128 tc->getITBPtr()->insert(alignedVaddr, entry);
129 }
130 }
131
132 void FakeDTLBFault::invoke(ThreadContext * tc)
133 {
134 DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
135 vaddr, tc->readPC());
136 Process *p = tc->getProcessPtr();
146 Addr paddr;
147 bool success = p->pTable->translate(vaddr, paddr);
137 TlbEntry entry;
138 bool success = p->pTable->lookup(vaddr, entry);
148 if(!success) {
149 p->checkAndAllocNextPage(vaddr);
139 if(!success) {
140 p->checkAndAllocNextPage(vaddr);
150 success = p->pTable->translate(vaddr, paddr);
141 success = p->pTable->lookup(vaddr, entry);
151 }
152 if(!success) {
153 panic("Tried to access unmapped address %#x.\n", vaddr);
154 } else {
142 }
143 if(!success) {
144 panic("Tried to access unmapped address %#x.\n", vaddr);
145 } else {
155 TlbEntry entry;
156 entry.pageStart = p->pTable->pageAlign(paddr);
157 entry.writeable = true;
158 entry.user = true;
159 entry.uncacheable = false;
160 entry.global = false;
161 entry.patBit = 0;
162 entry.noExec = true;
163 entry.size = PageBytes;
164 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
165 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
166 tc->getDTBPtr()->insert(alignedVaddr, entry);
167 }
168 }
169#endif
170} // namespace X86ISA
171
146 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
147 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
148 tc->getDTBPtr()->insert(alignedVaddr, entry);
149 }
150 }
151#endif
152} // namespace X86ISA
153