faults.cc (10100:24cfe67c0749) faults.cc (10417:710ee116eb68)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "arch/x86/isa_traits.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "arch/x86/isa_traits.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
53 void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
54 {
55 if (!FullSystem) {
56 FaultBase::invoke(tc, inst);
57 return;
58 }
59
60 PCState pcState = tc->pcState();
61 Addr pc = pcState.pc();

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99 ccprintf(ss, "%s", mnemonic());
100 if (errorCode != (uint64_t)(-1)) {
101 ccprintf(ss, "(%#x)", errorCode);
102 }
103
104 return ss.str();
105 }
106
54 {
55 if (!FullSystem) {
56 FaultBase::invoke(tc, inst);
57 return;
58 }
59
60 PCState pcState = tc->pcState();
61 Addr pc = pcState.pc();

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99 ccprintf(ss, "%s", mnemonic());
100 if (errorCode != (uint64_t)(-1)) {
101 ccprintf(ss, "(%#x)", errorCode);
102 }
103
104 return ss.str();
105 }
106
107 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
107 void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
108 {
109 X86FaultBase::invoke(tc);
110 if (!FullSystem)
111 return;
112
113 // This is the same as a fault, but it happens -after- the
114 // instruction.
115 PCState pc = tc->pcState();
116 pc.uEnd();
117 }
118
108 {
109 X86FaultBase::invoke(tc);
110 if (!FullSystem)
111 return;
112
113 // This is the same as a fault, but it happens -after- the
114 // instruction.
115 PCState pc = tc->pcState();
116 pc.uEnd();
117 }
118
119 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
119 void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst)
120 {
121 panic("Abort exception!");
122 }
123
124 void
120 {
121 panic("Abort exception!");
122 }
123
124 void
125 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
125 InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst)
126 {
127 if (FullSystem) {
128 X86Fault::invoke(tc, inst);
129 } else {
130 panic("Unrecognized/invalid instruction executed:\n %s",
131 inst->machInst);
132 }
133 }
134
126 {
127 if (FullSystem) {
128 X86Fault::invoke(tc, inst);
129 } else {
130 panic("Unrecognized/invalid instruction executed:\n %s",
131 inst->machInst);
132 }
133 }
134
135 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
135 void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
136 {
137 if (FullSystem) {
138 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
139 X86FaultBase::invoke(tc);
140 /*
141 * If something bad happens while trying to enter the page fault
142 * handler, I'm pretty sure that's a double fault and then all
143 * bets are off. That means it should be safe to update this

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165 PageFault::describe() const
166 {
167 std::stringstream ss;
168 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
169 return ss.str();
170 }
171
172 void
136 {
137 if (FullSystem) {
138 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
139 X86FaultBase::invoke(tc);
140 /*
141 * If something bad happens while trying to enter the page fault
142 * handler, I'm pretty sure that's a double fault and then all
143 * bets are off. That means it should be safe to update this

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165 PageFault::describe() const
166 {
167 std::stringstream ss;
168 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
169 return ss.str();
170 }
171
172 void
173 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
173 InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
174 {
175 DPRINTF(Faults, "Init interrupt.\n");
176 // The otherwise unmodified integer registers should be set to 0.
177 for (int index = 0; index < NUM_INTREGS; index++) {
178 tc->setIntReg(index, 0);
179 }
180
181 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);

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283 tc->setMiscReg(MISCREG_M5_REG, 0);
284 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
285 pc.upc(romMicroPC(entry));
286 pc.nupc(romMicroPC(entry) + 1);
287 tc->pcState(pc);
288 }
289
290 void
174 {
175 DPRINTF(Faults, "Init interrupt.\n");
176 // The otherwise unmodified integer registers should be set to 0.
177 for (int index = 0; index < NUM_INTREGS; index++) {
178 tc->setIntReg(index, 0);
179 }
180
181 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);

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283 tc->setMiscReg(MISCREG_M5_REG, 0);
284 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
285 pc.upc(romMicroPC(entry));
286 pc.nupc(romMicroPC(entry) + 1);
287 tc->pcState(pc);
288 }
289
290 void
291 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
291 StartupInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
292 {
293 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
294 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
295 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
296 panic("Startup IPI recived outside of real mode. "
297 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
298 }
299
300 tc->setMiscReg(MISCREG_CS, vector << 8);
301 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
302 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
303 // This has the base value pre-added.
304 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
305
306 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
307 }
308} // namespace X86ISA
309
292 {
293 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
294 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
295 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
296 panic("Startup IPI recived outside of real mode. "
297 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
298 }
299
300 tc->setMiscReg(MISCREG_CS, vector << 8);
301 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
302 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
303 // This has the base value pre-added.
304 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
305
306 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
307 }
308} // namespace X86ISA
309