faults.cc (8740:253aeee61e66) faults.cc (8806:669e93d79ed9)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/isa_traits.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
54 {
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/isa_traits.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
54 {
55 if (FullSystem) {
56 PCState pcState = tc->pcState();
57 Addr pc = pcState.pc();
58 DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
59 pc, vector, describe());
60 using namespace X86ISAInst::RomLabels;
61 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
62 MicroPC entry;
63 if (m5reg.mode == LongMode) {
64 if (isSoft()) {
65 entry = extern_label_longModeSoftInterrupt;
66 } else {
67 entry = extern_label_longModeInterrupt;
68 }
55 if (!FullSystem) {
56 FaultBase::invoke(tc, inst);
57 return;
58 }
59
60 PCState pcState = tc->pcState();
61 Addr pc = pcState.pc();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
63 pc, vector, describe());
64 using namespace X86ISAInst::RomLabels;
65 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
66 MicroPC entry;
67 if (m5reg.mode == LongMode) {
68 if (isSoft()) {
69 entry = extern_label_longModeSoftInterrupt;
69 } else {
70 } else {
70 entry = extern_label_legacyModeInterrupt;
71 entry = extern_label_longModeInterrupt;
71 }
72 }
72 tc->setIntReg(INTREG_MICRO(1), vector);
73 tc->setIntReg(INTREG_MICRO(7), pc);
74 if (errorCode != (uint64_t)(-1)) {
75 if (m5reg.mode == LongMode) {
76 entry = extern_label_longModeInterruptWithError;
77 } else {
78 panic("Legacy mode interrupts with error codes "
79 "aren't implementde.\n");
80 }
81 // Software interrupts shouldn't have error codes. If one
82 // does, there would need to be microcode to set it up.
83 assert(!isSoft());
84 tc->setIntReg(INTREG_MICRO(15), errorCode);
85 }
86 pcState.upc(romMicroPC(entry));
87 pcState.nupc(romMicroPC(entry) + 1);
88 tc->pcState(pcState);
89 } else {
73 } else {
90 FaultBase::invoke(tc, inst);
74 entry = extern_label_legacyModeInterrupt;
91 }
75 }
76 tc->setIntReg(INTREG_MICRO(1), vector);
77 tc->setIntReg(INTREG_MICRO(7), pc);
78 if (errorCode != (uint64_t)(-1)) {
79 if (m5reg.mode == LongMode) {
80 entry = extern_label_longModeInterruptWithError;
81 } else {
82 panic("Legacy mode interrupts with error codes "
83 "aren't implementde.\n");
84 }
85 // Software interrupts shouldn't have error codes. If one
86 // does, there would need to be microcode to set it up.
87 assert(!isSoft());
88 tc->setIntReg(INTREG_MICRO(15), errorCode);
89 }
90 pcState.upc(romMicroPC(entry));
91 pcState.nupc(romMicroPC(entry) + 1);
92 tc->pcState(pcState);
92 }
93
94 std::string
95 X86FaultBase::describe() const
96 {
97 std::stringstream ss;
98 ccprintf(ss, "%s", mnemonic());
99 if (errorCode != (uint64_t)(-1)) {
100 ccprintf(ss, "(%#x)", errorCode);
101 }
102
103 return ss.str();
104 }
105
106 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
107 {
108 X86FaultBase::invoke(tc);
93 }
94
95 std::string
96 X86FaultBase::describe() const
97 {
98 std::stringstream ss;
99 ccprintf(ss, "%s", mnemonic());
100 if (errorCode != (uint64_t)(-1)) {
101 ccprintf(ss, "(%#x)", errorCode);
102 }
103
104 return ss.str();
105 }
106
107 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
108 {
109 X86FaultBase::invoke(tc);
109 if (FullSystem) {
110 // This is the same as a fault, but it happens -after- the
111 // instruction.
112 PCState pc = tc->pcState();
113 pc.uEnd();
114 }
110 if (!FullSystem)
111 return;
112
113 // This is the same as a fault, but it happens -after- the
114 // instruction.
115 PCState pc = tc->pcState();
116 pc.uEnd();
115 }
116
117 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
118 {
119 panic("Abort exception!");
120 }
121
122 void
123 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
124 {
125 if (FullSystem) {
126 X86Fault::invoke(tc, inst);
127 } else {
128 panic("Unrecognized/invalid instruction executed:\n %s",
129 inst->machInst);
130 }
131 }
132
133 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
134 {
135 if (FullSystem) {
136 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
137 X86FaultBase::invoke(tc);
138 /*
139 * If something bad happens while trying to enter the page fault
140 * handler, I'm pretty sure that's a double fault and then all
141 * bets are off. That means it should be safe to update this
142 * state now.
143 */
144 if (m5reg.mode == LongMode) {
145 tc->setMiscReg(MISCREG_CR2, addr);
146 } else {
147 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
148 }
149 } else {
150 PageFaultErrorCode code = errorCode;
151 const char *modeStr = "";
152 if (code.fetch)
153 modeStr = "execute";
154 else if (code.write)
155 modeStr = "write";
156 else
157 modeStr = "read";
158 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
159 }
160 }
161
162 std::string
163 PageFault::describe() const
164 {
165 std::stringstream ss;
166 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
167 return ss.str();
168 }
169
170 void
171 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
172 {
173 DPRINTF(Faults, "Init interrupt.\n");
174 // The otherwise unmodified integer registers should be set to 0.
175 for (int index = 0; index < NUM_INTREGS; index++) {
176 tc->setIntReg(index, 0);
177 }
178
179 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
180 CR0 newCR0 = 1 << 4;
181 newCR0.cd = cr0.cd;
182 newCR0.nw = cr0.nw;
183 tc->setMiscReg(MISCREG_CR0, newCR0);
184 tc->setMiscReg(MISCREG_CR2, 0);
185 tc->setMiscReg(MISCREG_CR3, 0);
186 tc->setMiscReg(MISCREG_CR4, 0);
187
188 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
189
190 tc->setMiscReg(MISCREG_EFER, 0);
191
192 SegAttr dataAttr = 0;
193 dataAttr.dpl = 0;
194 dataAttr.unusable = 0;
195 dataAttr.defaultSize = 0;
196 dataAttr.longMode = 0;
197 dataAttr.avl = 0;
198 dataAttr.granularity = 0;
199 dataAttr.present = 1;
200 dataAttr.type = 3;
201 dataAttr.writable = 1;
202 dataAttr.readable = 1;
203 dataAttr.expandDown = 0;
204 dataAttr.system = 1;
205
206 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
207 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
208 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
209 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
210 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
211 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
212 }
213
214 SegAttr codeAttr = 0;
215 codeAttr.dpl = 0;
216 codeAttr.unusable = 0;
217 codeAttr.defaultSize = 0;
218 codeAttr.longMode = 0;
219 codeAttr.avl = 0;
220 codeAttr.granularity = 0;
221 codeAttr.present = 1;
222 codeAttr.type = 10;
223 codeAttr.writable = 0;
224 codeAttr.readable = 1;
225 codeAttr.expandDown = 0;
226 codeAttr.system = 1;
227
228 tc->setMiscReg(MISCREG_CS, 0xf000);
229 tc->setMiscReg(MISCREG_CS_BASE,
230 0x00000000ffff0000ULL);
231 tc->setMiscReg(MISCREG_CS_EFF_BASE,
232 0x00000000ffff0000ULL);
233 // This has the base value pre-added.
234 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
235 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
236
237 PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
238 tc->pcState(pc);
239
240 tc->setMiscReg(MISCREG_TSG_BASE, 0);
241 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
242
243 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
244 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
245
246 tc->setMiscReg(MISCREG_TSL, 0);
247 tc->setMiscReg(MISCREG_TSL_BASE, 0);
248 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
249 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
250
251 tc->setMiscReg(MISCREG_TR, 0);
252 tc->setMiscReg(MISCREG_TR_BASE, 0);
253 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
254 tc->setMiscReg(MISCREG_TR_ATTR, 0);
255
256 // This value should be the family/model/stepping of the processor.
257 // (page 418). It should be consistent with the value from CPUID, but
258 // the actual value probably doesn't matter much.
259 tc->setIntReg(INTREG_RDX, 0);
260
261 tc->setMiscReg(MISCREG_DR0, 0);
262 tc->setMiscReg(MISCREG_DR1, 0);
263 tc->setMiscReg(MISCREG_DR2, 0);
264 tc->setMiscReg(MISCREG_DR3, 0);
265
266 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
267 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
268
269 // Update the handy M5 Reg.
270 tc->setMiscReg(MISCREG_M5_REG, 0);
271 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
272 pc.upc(romMicroPC(entry));
273 pc.nupc(romMicroPC(entry) + 1);
274 tc->pcState(pc);
275 }
276
277 void
278 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
279 {
280 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
281 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
282 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
283 panic("Startup IPI recived outside of real mode. "
284 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
285 }
286
287 tc->setMiscReg(MISCREG_CS, vector << 8);
288 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
289 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
290 // This has the base value pre-added.
291 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
292
293 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
294 }
295} // namespace X86ISA
296
117 }
118
119 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
120 {
121 panic("Abort exception!");
122 }
123
124 void
125 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
126 {
127 if (FullSystem) {
128 X86Fault::invoke(tc, inst);
129 } else {
130 panic("Unrecognized/invalid instruction executed:\n %s",
131 inst->machInst);
132 }
133 }
134
135 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
136 {
137 if (FullSystem) {
138 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
139 X86FaultBase::invoke(tc);
140 /*
141 * If something bad happens while trying to enter the page fault
142 * handler, I'm pretty sure that's a double fault and then all
143 * bets are off. That means it should be safe to update this
144 * state now.
145 */
146 if (m5reg.mode == LongMode) {
147 tc->setMiscReg(MISCREG_CR2, addr);
148 } else {
149 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
150 }
151 } else {
152 PageFaultErrorCode code = errorCode;
153 const char *modeStr = "";
154 if (code.fetch)
155 modeStr = "execute";
156 else if (code.write)
157 modeStr = "write";
158 else
159 modeStr = "read";
160 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
161 }
162 }
163
164 std::string
165 PageFault::describe() const
166 {
167 std::stringstream ss;
168 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
169 return ss.str();
170 }
171
172 void
173 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
174 {
175 DPRINTF(Faults, "Init interrupt.\n");
176 // The otherwise unmodified integer registers should be set to 0.
177 for (int index = 0; index < NUM_INTREGS; index++) {
178 tc->setIntReg(index, 0);
179 }
180
181 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
182 CR0 newCR0 = 1 << 4;
183 newCR0.cd = cr0.cd;
184 newCR0.nw = cr0.nw;
185 tc->setMiscReg(MISCREG_CR0, newCR0);
186 tc->setMiscReg(MISCREG_CR2, 0);
187 tc->setMiscReg(MISCREG_CR3, 0);
188 tc->setMiscReg(MISCREG_CR4, 0);
189
190 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
191
192 tc->setMiscReg(MISCREG_EFER, 0);
193
194 SegAttr dataAttr = 0;
195 dataAttr.dpl = 0;
196 dataAttr.unusable = 0;
197 dataAttr.defaultSize = 0;
198 dataAttr.longMode = 0;
199 dataAttr.avl = 0;
200 dataAttr.granularity = 0;
201 dataAttr.present = 1;
202 dataAttr.type = 3;
203 dataAttr.writable = 1;
204 dataAttr.readable = 1;
205 dataAttr.expandDown = 0;
206 dataAttr.system = 1;
207
208 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
209 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
210 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
211 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
212 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
213 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
214 }
215
216 SegAttr codeAttr = 0;
217 codeAttr.dpl = 0;
218 codeAttr.unusable = 0;
219 codeAttr.defaultSize = 0;
220 codeAttr.longMode = 0;
221 codeAttr.avl = 0;
222 codeAttr.granularity = 0;
223 codeAttr.present = 1;
224 codeAttr.type = 10;
225 codeAttr.writable = 0;
226 codeAttr.readable = 1;
227 codeAttr.expandDown = 0;
228 codeAttr.system = 1;
229
230 tc->setMiscReg(MISCREG_CS, 0xf000);
231 tc->setMiscReg(MISCREG_CS_BASE,
232 0x00000000ffff0000ULL);
233 tc->setMiscReg(MISCREG_CS_EFF_BASE,
234 0x00000000ffff0000ULL);
235 // This has the base value pre-added.
236 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
237 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
238
239 PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
240 tc->pcState(pc);
241
242 tc->setMiscReg(MISCREG_TSG_BASE, 0);
243 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
244
245 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
246 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
247
248 tc->setMiscReg(MISCREG_TSL, 0);
249 tc->setMiscReg(MISCREG_TSL_BASE, 0);
250 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
251 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
252
253 tc->setMiscReg(MISCREG_TR, 0);
254 tc->setMiscReg(MISCREG_TR_BASE, 0);
255 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
256 tc->setMiscReg(MISCREG_TR_ATTR, 0);
257
258 // This value should be the family/model/stepping of the processor.
259 // (page 418). It should be consistent with the value from CPUID, but
260 // the actual value probably doesn't matter much.
261 tc->setIntReg(INTREG_RDX, 0);
262
263 tc->setMiscReg(MISCREG_DR0, 0);
264 tc->setMiscReg(MISCREG_DR1, 0);
265 tc->setMiscReg(MISCREG_DR2, 0);
266 tc->setMiscReg(MISCREG_DR3, 0);
267
268 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
269 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
270
271 // Update the handy M5 Reg.
272 tc->setMiscReg(MISCREG_M5_REG, 0);
273 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
274 pc.upc(romMicroPC(entry));
275 pc.nupc(romMicroPC(entry) + 1);
276 tc->pcState(pc);
277 }
278
279 void
280 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
281 {
282 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
283 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
284 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
285 panic("Startup IPI recived outside of real mode. "
286 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
287 }
288
289 tc->setMiscReg(MISCREG_CS, vector << 8);
290 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
291 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
292 // This has the base value pre-added.
293 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
294
295 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
296 }
297} // namespace X86ISA
298