1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "base/trace.hh"
46#include "config/full_system.hh"
47#include "cpu/thread_context.hh"
48#if !FULL_SYSTEM
49#include "arch/x86/isa_traits.hh"
50#include "mem/page_table.hh"
51#include "sim/process.hh"
52#else
53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "base/trace.hh"
46#include "config/full_system.hh"
47#include "cpu/thread_context.hh"
48#if !FULL_SYSTEM
49#include "arch/x86/isa_traits.hh"
50#include "mem/page_table.hh"
51#include "sim/process.hh"
52#else
53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
|
59 void X86FaultBase::invoke(ThreadContext * tc)
| 59 void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
|
60 {
61 Addr pc = tc->readPC();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
63 using namespace X86ISAInst::RomLabels;
64 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
65 MicroPC entry;
66 if (m5reg.mode == LongMode) {
67 if (isSoft()) {
68 entry = extern_label_longModeSoftInterrupt;
69 } else {
70 entry = extern_label_longModeInterrupt;
71 }
72 } else {
73 entry = extern_label_legacyModeInterrupt;
74 }
75 tc->setIntReg(INTREG_MICRO(1), vector);
76 tc->setIntReg(INTREG_MICRO(7), pc);
77 if (errorCode != (uint64_t)(-1)) {
78 if (m5reg.mode == LongMode) {
79 entry = extern_label_longModeInterruptWithError;
80 } else {
81 panic("Legacy mode interrupts with error codes "
82 "aren't implementde.\n");
83 }
84 // Software interrupts shouldn't have error codes. If one does,
85 // there would need to be microcode to set it up.
86 assert(!isSoft());
87 tc->setIntReg(INTREG_MICRO(15), errorCode);
88 }
89 tc->setMicroPC(romMicroPC(entry));
90 tc->setNextMicroPC(romMicroPC(entry) + 1);
91 }
92
93 std::string
94 X86FaultBase::describe() const
95 {
96 std::stringstream ss;
97 ccprintf(ss, "%s", mnemonic());
98 if (errorCode != (uint64_t)(-1)) {
99 ccprintf(ss, "(%#x)", errorCode);
100 }
101
102 return ss.str();
103 }
104
| 60 {
61 Addr pc = tc->readPC();
62 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
63 using namespace X86ISAInst::RomLabels;
64 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
65 MicroPC entry;
66 if (m5reg.mode == LongMode) {
67 if (isSoft()) {
68 entry = extern_label_longModeSoftInterrupt;
69 } else {
70 entry = extern_label_longModeInterrupt;
71 }
72 } else {
73 entry = extern_label_legacyModeInterrupt;
74 }
75 tc->setIntReg(INTREG_MICRO(1), vector);
76 tc->setIntReg(INTREG_MICRO(7), pc);
77 if (errorCode != (uint64_t)(-1)) {
78 if (m5reg.mode == LongMode) {
79 entry = extern_label_longModeInterruptWithError;
80 } else {
81 panic("Legacy mode interrupts with error codes "
82 "aren't implementde.\n");
83 }
84 // Software interrupts shouldn't have error codes. If one does,
85 // there would need to be microcode to set it up.
86 assert(!isSoft());
87 tc->setIntReg(INTREG_MICRO(15), errorCode);
88 }
89 tc->setMicroPC(romMicroPC(entry));
90 tc->setNextMicroPC(romMicroPC(entry) + 1);
91 }
92
93 std::string
94 X86FaultBase::describe() const
95 {
96 std::stringstream ss;
97 ccprintf(ss, "%s", mnemonic());
98 if (errorCode != (uint64_t)(-1)) {
99 ccprintf(ss, "(%#x)", errorCode);
100 }
101
102 return ss.str();
103 }
104
|
105 void X86Trap::invoke(ThreadContext * tc)
| 105 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
|
106 {
107 X86FaultBase::invoke(tc);
108 // This is the same as a fault, but it happens -after- the instruction.
109 tc->setPC(tc->readNextPC());
110 tc->setNextPC(tc->readNextNPC());
111 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
112 }
113
| 106 {
107 X86FaultBase::invoke(tc);
108 // This is the same as a fault, but it happens -after- the instruction.
109 tc->setPC(tc->readNextPC());
110 tc->setNextPC(tc->readNextNPC());
111 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
112 }
113
|
114 void X86Abort::invoke(ThreadContext * tc)
| 114 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
|
115 {
116 panic("Abort exception!");
117 }
118
| 115 {
116 panic("Abort exception!");
117 }
118
|
119 void PageFault::invoke(ThreadContext * tc)
| 119 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
|
120 {
121 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
122 X86FaultBase::invoke(tc);
123 /*
124 * If something bad happens while trying to enter the page fault
125 * handler, I'm pretty sure that's a double fault and then all bets are
126 * off. That means it should be safe to update this state now.
127 */
128 if (m5reg.mode == LongMode) {
129 tc->setMiscReg(MISCREG_CR2, addr);
130 } else {
131 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
132 }
133 }
134
135 std::string
136 PageFault::describe() const
137 {
138 std::stringstream ss;
139 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
140 return ss.str();
141 }
142
143 void
| 120 {
121 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
122 X86FaultBase::invoke(tc);
123 /*
124 * If something bad happens while trying to enter the page fault
125 * handler, I'm pretty sure that's a double fault and then all bets are
126 * off. That means it should be safe to update this state now.
127 */
128 if (m5reg.mode == LongMode) {
129 tc->setMiscReg(MISCREG_CR2, addr);
130 } else {
131 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
132 }
133 }
134
135 std::string
136 PageFault::describe() const
137 {
138 std::stringstream ss;
139 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
140 return ss.str();
141 }
142
143 void
|
144 InitInterrupt::invoke(ThreadContext *tc)
| 144 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
|
145 {
146 DPRINTF(Faults, "Init interrupt.\n");
147 // The otherwise unmodified integer registers should be set to 0.
148 for (int index = 0; index < NUM_INTREGS; index++) {
149 tc->setIntReg(index, 0);
150 }
151
152 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
153 CR0 newCR0 = 1 << 4;
154 newCR0.cd = cr0.cd;
155 newCR0.nw = cr0.nw;
156 tc->setMiscReg(MISCREG_CR0, newCR0);
157 tc->setMiscReg(MISCREG_CR2, 0);
158 tc->setMiscReg(MISCREG_CR3, 0);
159 tc->setMiscReg(MISCREG_CR4, 0);
160
161 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
162
163 tc->setMiscReg(MISCREG_EFER, 0);
164
165 SegAttr dataAttr = 0;
166 dataAttr.dpl = 0;
167 dataAttr.unusable = 0;
168 dataAttr.defaultSize = 0;
169 dataAttr.longMode = 0;
170 dataAttr.avl = 0;
171 dataAttr.granularity = 0;
172 dataAttr.present = 1;
173 dataAttr.type = 3;
174 dataAttr.writable = 1;
175 dataAttr.readable = 1;
176 dataAttr.expandDown = 0;
177 dataAttr.system = 1;
178
179 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
180 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
181 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
182 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
183 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
184 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
185 }
186
187 SegAttr codeAttr = 0;
188 codeAttr.dpl = 0;
189 codeAttr.unusable = 0;
190 codeAttr.defaultSize = 0;
191 codeAttr.longMode = 0;
192 codeAttr.avl = 0;
193 codeAttr.granularity = 0;
194 codeAttr.present = 1;
195 codeAttr.type = 10;
196 codeAttr.writable = 0;
197 codeAttr.readable = 1;
198 codeAttr.expandDown = 0;
199 codeAttr.system = 1;
200
201 tc->setMiscReg(MISCREG_CS, 0xf000);
202 tc->setMiscReg(MISCREG_CS_BASE,
203 0x00000000ffff0000ULL);
204 tc->setMiscReg(MISCREG_CS_EFF_BASE,
205 0x00000000ffff0000ULL);
206 // This has the base value pre-added.
207 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
208 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
209
210 tc->setPC(0x000000000000fff0ULL +
211 tc->readMiscReg(MISCREG_CS_BASE));
212 tc->setNextPC(tc->readPC() + sizeof(MachInst));
213
214 tc->setMiscReg(MISCREG_TSG_BASE, 0);
215 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
216
217 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
218 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
219
220 tc->setMiscReg(MISCREG_TSL, 0);
221 tc->setMiscReg(MISCREG_TSL_BASE, 0);
222 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
223 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
224
225 tc->setMiscReg(MISCREG_TR, 0);
226 tc->setMiscReg(MISCREG_TR_BASE, 0);
227 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
228 tc->setMiscReg(MISCREG_TR_ATTR, 0);
229
230 // This value should be the family/model/stepping of the processor.
231 // (page 418). It should be consistent with the value from CPUID, but
232 // the actual value probably doesn't matter much.
233 tc->setIntReg(INTREG_RDX, 0);
234
235 tc->setMiscReg(MISCREG_DR0, 0);
236 tc->setMiscReg(MISCREG_DR1, 0);
237 tc->setMiscReg(MISCREG_DR2, 0);
238 tc->setMiscReg(MISCREG_DR3, 0);
239
240 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
241 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
242
243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246 tc->setMicroPC(romMicroPC(entry));
247 tc->setNextMicroPC(romMicroPC(entry) + 1);
248 }
249
250 void
| 145 {
146 DPRINTF(Faults, "Init interrupt.\n");
147 // The otherwise unmodified integer registers should be set to 0.
148 for (int index = 0; index < NUM_INTREGS; index++) {
149 tc->setIntReg(index, 0);
150 }
151
152 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
153 CR0 newCR0 = 1 << 4;
154 newCR0.cd = cr0.cd;
155 newCR0.nw = cr0.nw;
156 tc->setMiscReg(MISCREG_CR0, newCR0);
157 tc->setMiscReg(MISCREG_CR2, 0);
158 tc->setMiscReg(MISCREG_CR3, 0);
159 tc->setMiscReg(MISCREG_CR4, 0);
160
161 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
162
163 tc->setMiscReg(MISCREG_EFER, 0);
164
165 SegAttr dataAttr = 0;
166 dataAttr.dpl = 0;
167 dataAttr.unusable = 0;
168 dataAttr.defaultSize = 0;
169 dataAttr.longMode = 0;
170 dataAttr.avl = 0;
171 dataAttr.granularity = 0;
172 dataAttr.present = 1;
173 dataAttr.type = 3;
174 dataAttr.writable = 1;
175 dataAttr.readable = 1;
176 dataAttr.expandDown = 0;
177 dataAttr.system = 1;
178
179 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
180 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
181 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
182 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
183 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
184 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
185 }
186
187 SegAttr codeAttr = 0;
188 codeAttr.dpl = 0;
189 codeAttr.unusable = 0;
190 codeAttr.defaultSize = 0;
191 codeAttr.longMode = 0;
192 codeAttr.avl = 0;
193 codeAttr.granularity = 0;
194 codeAttr.present = 1;
195 codeAttr.type = 10;
196 codeAttr.writable = 0;
197 codeAttr.readable = 1;
198 codeAttr.expandDown = 0;
199 codeAttr.system = 1;
200
201 tc->setMiscReg(MISCREG_CS, 0xf000);
202 tc->setMiscReg(MISCREG_CS_BASE,
203 0x00000000ffff0000ULL);
204 tc->setMiscReg(MISCREG_CS_EFF_BASE,
205 0x00000000ffff0000ULL);
206 // This has the base value pre-added.
207 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
208 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
209
210 tc->setPC(0x000000000000fff0ULL +
211 tc->readMiscReg(MISCREG_CS_BASE));
212 tc->setNextPC(tc->readPC() + sizeof(MachInst));
213
214 tc->setMiscReg(MISCREG_TSG_BASE, 0);
215 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
216
217 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
218 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
219
220 tc->setMiscReg(MISCREG_TSL, 0);
221 tc->setMiscReg(MISCREG_TSL_BASE, 0);
222 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
223 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
224
225 tc->setMiscReg(MISCREG_TR, 0);
226 tc->setMiscReg(MISCREG_TR_BASE, 0);
227 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
228 tc->setMiscReg(MISCREG_TR_ATTR, 0);
229
230 // This value should be the family/model/stepping of the processor.
231 // (page 418). It should be consistent with the value from CPUID, but
232 // the actual value probably doesn't matter much.
233 tc->setIntReg(INTREG_RDX, 0);
234
235 tc->setMiscReg(MISCREG_DR0, 0);
236 tc->setMiscReg(MISCREG_DR1, 0);
237 tc->setMiscReg(MISCREG_DR2, 0);
238 tc->setMiscReg(MISCREG_DR3, 0);
239
240 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
241 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
242
243 // Update the handy M5 Reg.
244 tc->setMiscReg(MISCREG_M5_REG, 0);
245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246 tc->setMicroPC(romMicroPC(entry));
247 tc->setNextMicroPC(romMicroPC(entry) + 1);
248 }
249
250 void
|
251 StartupInterrupt::invoke(ThreadContext *tc)
| 251 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
|
252 {
253 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
254 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
255 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
258 }
259
260 tc->setMiscReg(MISCREG_CS, vector << 8);
261 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
262 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
263 // This has the base value pre-added.
264 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
265
266 tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
267 tc->setNextPC(tc->readPC() + sizeof(MachInst));
268 }
269
270#else
271
272 void
| 252 {
253 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
254 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
255 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
256 panic("Startup IPI recived outside of real mode. "
257 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
258 }
259
260 tc->setMiscReg(MISCREG_CS, vector << 8);
261 tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
262 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
263 // This has the base value pre-added.
264 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
265
266 tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
267 tc->setNextPC(tc->readPC() + sizeof(MachInst));
268 }
269
270#else
271
272 void
|
273 PageFault::invoke(ThreadContext * tc)
| 273 PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
|
274 {
275 PageFaultErrorCode code = errorCode;
276 const char *modeStr = "";
277 if (code.fetch)
278 modeStr = "execute";
279 else if (code.write)
280 modeStr = "write";
281 else
282 modeStr = "read";
283 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
284 }
285
286#endif
287} // namespace X86ISA
288
| 274 {
275 PageFaultErrorCode code = errorCode;
276 const char *modeStr = "";
277 if (code.fetch)
278 modeStr = "execute";
279 else if (code.write)
280 modeStr = "write";
281 else
282 modeStr = "read";
283 panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
284 }
285
286#endif
287} // namespace X86ISA
288
|