1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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88#include "arch/x86/faults.hh"
89#include "base/trace.hh"
90#include "config/full_system.hh"
91#include "cpu/thread_context.hh"
92#if !FULL_SYSTEM
93#include "arch/x86/isa_traits.hh"
94#include "mem/page_table.hh"
95#include "sim/process.hh"
96#endif
97
98namespace X86ISA
99{
100#if FULL_SYSTEM
101 void X86Trap::invoke(ThreadContext * tc)
102 {
103 panic("X86 faults are not implemented!");
104 }
105
106 void X86Abort::invoke(ThreadContext * tc)
107 {
108 panic("X86 faults are not implemented!");
109 }
110
111 void X86Interrupt::invoke(ThreadContext * tc)
112 {
113 panic("X86 faults are not implemented!");
114 }
115#else // !FULL_SYSTEM
116 void FakeITLBFault::invoke(ThreadContext * tc)
117 {
118 DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
119 vaddr, tc->readPC());
120 Process *p = tc->getProcessPtr();
121 TlbEntry entry;
122 bool success = p->pTable->lookup(vaddr, entry);

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