1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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119 vaddr, tc->readPC());
120 Process *p = tc->getProcessPtr();
121 TlbEntry entry;
122 bool success = p->pTable->lookup(vaddr, entry);
123 if(!success) {
124 panic("Tried to execute unmapped address %#x.\n", vaddr);
125 } else {
126 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
127 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
128 tc->getITBPtr()->insert(alignedVaddr, entry);
129 }
130 }
131
132 void FakeDTLBFault::invoke(ThreadContext * tc)
133 {
134 DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
135 vaddr, tc->readPC());
136 Process *p = tc->getProcessPtr();
137 TlbEntry entry;
138 bool success = p->pTable->lookup(vaddr, entry);
139 if(!success) {
140 p->checkAndAllocNextPage(vaddr);
141 success = p->pTable->lookup(vaddr, entry);
142 }
143 if(!success) {
144 panic("Tried to access unmapped address %#x.\n", vaddr);
145 } else {
146 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
147 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
148 tc->getDTBPtr()->insert(alignedVaddr, entry);
149 }
150 }
151#endif
152} // namespace X86ISA
153