IntelMP.py (7087:fb8d5786ff30) IntelMP.py (9338:97b4a2be1e5b)
1# Copyright (c) 2008 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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36# Authors: Gabe Black
37
38from m5.params import *
39from m5.SimObject import SimObject
40
41class X86IntelMPFloatingPointer(SimObject):
42 type = 'X86IntelMPFloatingPointer'
43 cxx_class = 'X86ISA::IntelMP::FloatingPointer'
1# Copyright (c) 2008 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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36# Authors: Gabe Black
37
38from m5.params import *
39from m5.SimObject import SimObject
40
41class X86IntelMPFloatingPointer(SimObject):
42 type = 'X86IntelMPFloatingPointer'
43 cxx_class = 'X86ISA::IntelMP::FloatingPointer'
44 cxx_header = 'arch/x86/bios/intelmp.hh'
44
45 # The minor revision of the spec to support. The major version is assumed
46 # to be 1 in accordance with the spec.
47 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
48 # If no default configuration is used, set this to 0.
49 default_config = Param.UInt8(0, 'which default configuration to use')
50 imcr_present = Param.Bool(True,
51 'whether the IMCR register is present in the APIC')
52
53class X86IntelMPConfigTable(SimObject):
54 type = 'X86IntelMPConfigTable'
55 cxx_class = 'X86ISA::IntelMP::ConfigTable'
45
46 # The minor revision of the spec to support. The major version is assumed
47 # to be 1 in accordance with the spec.
48 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
49 # If no default configuration is used, set this to 0.
50 default_config = Param.UInt8(0, 'which default configuration to use')
51 imcr_present = Param.Bool(True,
52 'whether the IMCR register is present in the APIC')
53
54class X86IntelMPConfigTable(SimObject):
55 type = 'X86IntelMPConfigTable'
56 cxx_class = 'X86ISA::IntelMP::ConfigTable'
57 cxx_header = 'arch/x86/bios/intelmp.hh'
56
57 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
58 oem_id = Param.String("", 'system manufacturer')
59 product_id = Param.String("", 'product family')
60 oem_table_addr = Param.UInt32(0,
61 'pointer to the optional oem configuration table')
62 oem_table_size = Param.UInt16(0, 'size of the oem configuration table')
63 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC')

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75 self.ext_entries.append(entry)
76 else:
77 panic("Don't know what type of Intel MP entry %s is." \
78 % entry.__class__.__name__)
79
80class X86IntelMPBaseConfigEntry(SimObject):
81 type = 'X86IntelMPBaseConfigEntry'
82 cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
58
59 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
60 oem_id = Param.String("", 'system manufacturer')
61 product_id = Param.String("", 'product family')
62 oem_table_addr = Param.UInt32(0,
63 'pointer to the optional oem configuration table')
64 oem_table_size = Param.UInt16(0, 'size of the oem configuration table')
65 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC')

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77 self.ext_entries.append(entry)
78 else:
79 panic("Don't know what type of Intel MP entry %s is." \
80 % entry.__class__.__name__)
81
82class X86IntelMPBaseConfigEntry(SimObject):
83 type = 'X86IntelMPBaseConfigEntry'
84 cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
85 cxx_header = 'arch/x86/bios/intelmp.hh'
83 abstract = True
84
85class X86IntelMPExtConfigEntry(SimObject):
86 type = 'X86IntelMPExtConfigEntry'
87 cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
86 abstract = True
87
88class X86IntelMPExtConfigEntry(SimObject):
89 type = 'X86IntelMPExtConfigEntry'
90 cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
91 cxx_header = 'arch/x86/bios/intelmp.hh'
88 abstract = True
89
90class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
91 type = 'X86IntelMPProcessor'
92 cxx_class = 'X86ISA::IntelMP::Processor'
92 abstract = True
93
94class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
95 type = 'X86IntelMPProcessor'
96 cxx_class = 'X86ISA::IntelMP::Processor'
97 cxx_header = 'arch/x86/bios/intelmp.hh'
93
94 local_apic_id = Param.UInt8(0, 'local APIC id')
95 local_apic_version = Param.UInt8(0,
96 'bits 0-7 of the local APIC version register')
97 enable = Param.Bool(True, 'if this processor is usable')
98 bootstrap = Param.Bool(False, 'if this is the bootstrap processor')
99
100 stepping = Param.UInt8(0, 'Processor stepping')
101 model = Param.UInt8(0, 'Processor model')
102 family = Param.UInt8(0, 'Processor family')
103
104 feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction')
105
106class X86IntelMPBus(X86IntelMPBaseConfigEntry):
107 type = 'X86IntelMPBus'
108 cxx_class = 'X86ISA::IntelMP::Bus'
98
99 local_apic_id = Param.UInt8(0, 'local APIC id')
100 local_apic_version = Param.UInt8(0,
101 'bits 0-7 of the local APIC version register')
102 enable = Param.Bool(True, 'if this processor is usable')
103 bootstrap = Param.Bool(False, 'if this is the bootstrap processor')
104
105 stepping = Param.UInt8(0, 'Processor stepping')
106 model = Param.UInt8(0, 'Processor model')
107 family = Param.UInt8(0, 'Processor family')
108
109 feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction')
110
111class X86IntelMPBus(X86IntelMPBaseConfigEntry):
112 type = 'X86IntelMPBus'
113 cxx_class = 'X86ISA::IntelMP::Bus'
114 cxx_header = 'arch/x86/bios/intelmp.hh'
109
110 bus_id = Param.UInt8(0, 'bus id assigned by the bios')
111 bus_type = Param.String("", 'string that identify the bus type')
112 # Legal values for bus_type are:
113 #
114 # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII",
115 # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME",
116 # "XPRESS"
117
118class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
119 type = 'X86IntelMPIOAPIC'
120 cxx_class = 'X86ISA::IntelMP::IOAPIC'
115
116 bus_id = Param.UInt8(0, 'bus id assigned by the bios')
117 bus_type = Param.String("", 'string that identify the bus type')
118 # Legal values for bus_type are:
119 #
120 # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII",
121 # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME",
122 # "XPRESS"
123
124class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
125 type = 'X86IntelMPIOAPIC'
126 cxx_class = 'X86ISA::IntelMP::IOAPIC'
127 cxx_header = 'arch/x86/bios/intelmp.hh'
121
122 id = Param.UInt8(0, 'id of this APIC')
123 version = Param.UInt8(0, 'bits 0-7 of the version register')
124
125 enable = Param.Bool(True, 'if this APIC is usable')
126
127 address = Param.UInt32(0xfec00000, 'address of this APIC')
128

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143 map = {'ConformTrigger' : 0,
144 'EdgeTrigger' : 1,
145 'LevelTrigger' : 3
146 }
147
148class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
149 type = 'X86IntelMPIOIntAssignment'
150 cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
128
129 id = Param.UInt8(0, 'id of this APIC')
130 version = Param.UInt8(0, 'bits 0-7 of the version register')
131
132 enable = Param.Bool(True, 'if this APIC is usable')
133
134 address = Param.UInt32(0xfec00000, 'address of this APIC')
135

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150 map = {'ConformTrigger' : 0,
151 'EdgeTrigger' : 1,
152 'LevelTrigger' : 3
153 }
154
155class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
156 type = 'X86IntelMPIOIntAssignment'
157 cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
158 cxx_header = 'arch/x86/bios/intelmp.hh'
151
152 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
153
154 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
155 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
156
157 source_bus_id = Param.UInt8(0,
158 'id of the bus from which the interrupt signal comes')
159 source_bus_irq = Param.UInt8(0,
160 'which interrupt signal from the source bus')
161
162 dest_io_apic_id = Param.UInt8(0,
163 'id of the IO APIC the interrupt is going to')
164 dest_io_apic_intin = Param.UInt8(0,
165 'the INTIN pin on the IO APIC the interrupt is connected to')
166
167class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
168 type = 'X86IntelMPLocalIntAssignment'
169 cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
159
160 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
161
162 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
163 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
164
165 source_bus_id = Param.UInt8(0,
166 'id of the bus from which the interrupt signal comes')
167 source_bus_irq = Param.UInt8(0,
168 'which interrupt signal from the source bus')
169
170 dest_io_apic_id = Param.UInt8(0,
171 'id of the IO APIC the interrupt is going to')
172 dest_io_apic_intin = Param.UInt8(0,
173 'the INTIN pin on the IO APIC the interrupt is connected to')
174
175class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
176 type = 'X86IntelMPLocalIntAssignment'
177 cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
178 cxx_header = 'arch/x86/bios/intelmp.hh'
170
171 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
172
173 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
174 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
175
176 source_bus_id = Param.UInt8(0,
177 'id of the bus from which the interrupt signal comes')

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187 map = {"IOAddress" : 0,
188 "MemoryAddress" : 1,
189 "PrefetchAddress" : 2
190 }
191
192class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
193 type = 'X86IntelMPAddrSpaceMapping'
194 cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
179
180 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
181
182 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
183 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
184
185 source_bus_id = Param.UInt8(0,
186 'id of the bus from which the interrupt signal comes')

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196 map = {"IOAddress" : 0,
197 "MemoryAddress" : 1,
198 "PrefetchAddress" : 2
199 }
200
201class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
202 type = 'X86IntelMPAddrSpaceMapping'
203 cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
204 cxx_header = 'arch/x86/bios/intelmp.hh'
195
196 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
197 address_type = Param.X86IntelMPAddressType('IOAddress',
198 'address type used to access bus')
199 address = Param.Addr(0, 'starting address of the mapping')
200 length = Param.UInt64(0, 'length of mapping in bytes')
201
202class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
203 type = 'X86IntelMPBusHierarchy'
204 cxx_class = 'X86ISA::IntelMP::BusHierarchy'
205
206 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
207 address_type = Param.X86IntelMPAddressType('IOAddress',
208 'address type used to access bus')
209 address = Param.Addr(0, 'starting address of the mapping')
210 length = Param.UInt64(0, 'length of mapping in bytes')
211
212class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
213 type = 'X86IntelMPBusHierarchy'
214 cxx_class = 'X86ISA::IntelMP::BusHierarchy'
215 cxx_header = 'arch/x86/bios/intelmp.hh'
205
206 bus_id = Param.UInt8(0, 'id of the bus being described')
207 subtractive_decode = Param.Bool(False,
208 'whether this bus contains all addresses not used by its children')
209 parent_bus = Param.UInt8(0, 'bus id of this busses parent')
210
211class X86IntelMPRangeList(Enum):
212 map = {"ISACompatible" : 0,
213 "VGACompatible" : 1
214 }
215
216class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
217 type = 'X86IntelMPCompatAddrSpaceMod'
218 cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
216
217 bus_id = Param.UInt8(0, 'id of the bus being described')
218 subtractive_decode = Param.Bool(False,
219 'whether this bus contains all addresses not used by its children')
220 parent_bus = Param.UInt8(0, 'bus id of this busses parent')
221
222class X86IntelMPRangeList(Enum):
223 map = {"ISACompatible" : 0,
224 "VGACompatible" : 1
225 }
226
227class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
228 type = 'X86IntelMPCompatAddrSpaceMod'
229 cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
230 cxx_header = 'arch/x86/bios/intelmp.hh'
219
220 bus_id = Param.UInt8(0, 'id of the bus being described')
221 add = Param.Bool(False,
222 'if the range should be added to the original mapping')
223 range_list = Param.X86IntelMPRangeList('ISACompatible',
224 'which predefined range of addresses to use')
231
232 bus_id = Param.UInt8(0, 'id of the bus being described')
233 add = Param.Bool(False,
234 'if the range should be added to the original mapping')
235 range_list = Param.X86IntelMPRangeList('ISACompatible',
236 'which predefined range of addresses to use')