1# Copyright (c) 2008 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38from m5.params import *
39from m5.SimObject import SimObject
40
41class X86IntelMPFloatingPointer(SimObject):
42 type = 'X86IntelMPFloatingPointer'
43 cxx_class = 'X86ISA::IntelMP::FloatingPointer'
44
45 # The minor revision of the spec to support. The major version is assumed
46 # to be 1 in accordance with the spec.
47 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
48 # If no default configuration is used, set this to 0.
49 default_config = Param.UInt8(0, 'which default configuration to use')
50 imcr_present = Param.Bool(True,
51 'whether the IMCR register is present in the APIC')
52
53class X86IntelMPConfigTable(SimObject):
54 type = 'X86IntelMPConfigTable'
55 cxx_class = 'X86ISA::IntelMP::ConfigTable'
56
57 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
58 oem_id = Param.String("", 'system manufacturer')
59 product_id = Param.String("", 'product family')
60 oem_table_addr = Param.UInt32(0,
61 'pointer to the optional oem configuration table')
62 oem_table_size = Param.UInt16(0, 'size of the oem configuration table')
63 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC')
64
65 base_entries = VectorParam.X86IntelMPBaseConfigEntry([],
66 'base configuration table entries')
67
68 ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
69 'extended configuration table entries')
70
71 def add_entry(self, entry):
72 if isinstance(entry, X86IntelMPBaseConfigEntry):
73 self.base_entries.append(entry)
74 elif isinstance(entry, X86IntelMPExtConfigEntry):
75 self.ext_entries.append(entry)
76 else:
77 panic("Don't know what type of Intel MP entry %s is." \
78 % entry.__class__.__name__)
79
80class X86IntelMPBaseConfigEntry(SimObject):
81 type = 'X86IntelMPBaseConfigEntry'
82 cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
83 abstract = True
84
85class X86IntelMPExtConfigEntry(SimObject):
86 type = 'X86IntelMPExtConfigEntry'
87 cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
88 abstract = True
89
90class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
91 type = 'X86IntelMPProcessor'
92 cxx_class = 'X86ISA::IntelMP::Processor'
93
94 local_apic_id = Param.UInt8(0, 'local APIC id')
95 local_apic_version = Param.UInt8(0,
96 'bits 0-7 of the local APIC version register')
97 enable = Param.Bool(True, 'if this processor is usable')
98 bootstrap = Param.Bool(False, 'if this is the bootstrap processor')
99
100 stepping = Param.UInt8(0, 'Processor stepping')
101 model = Param.UInt8(0, 'Processor model')
102 family = Param.UInt8(0, 'Processor family')
103
104 feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction')
105
106class X86IntelMPBus(X86IntelMPBaseConfigEntry):
107 type = 'X86IntelMPBus'
108 cxx_class = 'X86ISA::IntelMP::Bus'
109
110 bus_id = Param.UInt8(0, 'bus id assigned by the bios')
111 bus_type = Param.String("", 'string that identify the bus type')
112 # Legal values for bus_type are:
113 #
114 # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII",
115 # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME",
116 # "XPRESS"
117
118class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
119 type = 'X86IntelMPIOAPIC'
120 cxx_class = 'X86ISA::IntelMP::IOAPIC'
121
122 id = Param.UInt8(0, 'id of this APIC')
123 version = Param.UInt8(0, 'bits 0-7 of the version register')
124
125 enable = Param.Bool(True, 'if this APIC is usable')
126
127 address = Param.UInt32(0xfec00000, 'address of this APIC')
128
129class X86IntelMPInterruptType(Enum):
130 map = {'INT' : 0,
131 'NMI' : 1,
132 'SMI' : 2,
133 'ExtInt' : 3
134 }
135
136class X86IntelMPPolarity(Enum):
137 map = {'ConformPolarity' : 0,
138 'ActiveHigh' : 1,
139 'ActiveLow' : 3
140 }
141
142class X86IntelMPTriggerMode(Enum):
143 map = {'ConformTrigger' : 0,
144 'EdgeTrigger' : 1,
145 'LevelTrigger' : 3
146 }
147
148class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
149 type = 'X86IntelMPIOIntAssignment'
150 cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
151
152 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
153
154 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
155 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
156
157 source_bus_id = Param.UInt8(0,
158 'id of the bus from which the interrupt signal comes')
159 source_bus_irq = Param.UInt8(0,
160 'which interrupt signal from the source bus')
161
162 dest_io_apic_id = Param.UInt8(0,
163 'id of the IO APIC the interrupt is going to')
164 dest_io_apic_intin = Param.UInt8(0,
165 'the INTIN pin on the IO APIC the interrupt is connected to')
166
167class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
168 type = 'X86IntelMPLocalIntAssignment'
169 cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
170
171 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
172
173 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
174 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
175
176 source_bus_id = Param.UInt8(0,
177 'id of the bus from which the interrupt signal comes')
178 source_bus_irq = Param.UInt8(0,
179 'which interrupt signal from the source bus')
180
181 dest_local_apic_id = Param.UInt8(0,
182 'id of the local APIC the interrupt is going to')
183 dest_local_apic_intin = Param.UInt8(0,
184 'the INTIN pin on the local APIC the interrupt is connected to')
185
186class X86IntelMPAddressType(Enum):
187 map = {"IOAddress" : 0,
188 "MemoryAddress" : 1,
189 "PrefetchAddress" : 2
190 }
191
192class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
193 type = 'X86IntelMPAddrSpaceMapping'
194 cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
195
196 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
197 address_type = Param.X86IntelMPAddressType('IOAddress',
198 'address type used to access bus')
199 address = Param.Addr(0, 'starting address of the mapping')
200 length = Param.UInt64(0, 'length of mapping in bytes')
201
202class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
203 type = 'X86IntelMPBusHierarchy'
204 cxx_class = 'X86ISA::IntelMP::BusHierarchy'
205
206 bus_id = Param.UInt8(0, 'id of the bus being described')
207 subtractive_decode = Param.Bool(False,
208 'whether this bus contains all addresses not used by its children')
209 parent_bus = Param.UInt8(0, 'bus id of this busses parent')
210
211class X86IntelMPRangeList(Enum):
212 map = {"ISACompatible" : 0,
213 "VGACompatible" : 1
214 }
215
216class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
217 type = 'X86IntelMPCompatAddrSpaceMod'
218 cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
219
220 bus_id = Param.UInt8(0, 'id of the bus being described')
221 add = Param.Bool(False,
222 'if the range should be added to the original mapping')
223 range_list = Param.X86IntelMPRangeList('ISACompatible',
224 'which predefined range of addresses to use')
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38from m5.params import *
39from m5.SimObject import SimObject
40
41class X86IntelMPFloatingPointer(SimObject):
42 type = 'X86IntelMPFloatingPointer'
43 cxx_class = 'X86ISA::IntelMP::FloatingPointer'
44
45 # The minor revision of the spec to support. The major version is assumed
46 # to be 1 in accordance with the spec.
47 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
48 # If no default configuration is used, set this to 0.
49 default_config = Param.UInt8(0, 'which default configuration to use')
50 imcr_present = Param.Bool(True,
51 'whether the IMCR register is present in the APIC')
52
53class X86IntelMPConfigTable(SimObject):
54 type = 'X86IntelMPConfigTable'
55 cxx_class = 'X86ISA::IntelMP::ConfigTable'
56
57 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
58 oem_id = Param.String("", 'system manufacturer')
59 product_id = Param.String("", 'product family')
60 oem_table_addr = Param.UInt32(0,
61 'pointer to the optional oem configuration table')
62 oem_table_size = Param.UInt16(0, 'size of the oem configuration table')
63 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC')
64
65 base_entries = VectorParam.X86IntelMPBaseConfigEntry([],
66 'base configuration table entries')
67
68 ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
69 'extended configuration table entries')
70
71 def add_entry(self, entry):
72 if isinstance(entry, X86IntelMPBaseConfigEntry):
73 self.base_entries.append(entry)
74 elif isinstance(entry, X86IntelMPExtConfigEntry):
75 self.ext_entries.append(entry)
76 else:
77 panic("Don't know what type of Intel MP entry %s is." \
78 % entry.__class__.__name__)
79
80class X86IntelMPBaseConfigEntry(SimObject):
81 type = 'X86IntelMPBaseConfigEntry'
82 cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
83 abstract = True
84
85class X86IntelMPExtConfigEntry(SimObject):
86 type = 'X86IntelMPExtConfigEntry'
87 cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
88 abstract = True
89
90class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
91 type = 'X86IntelMPProcessor'
92 cxx_class = 'X86ISA::IntelMP::Processor'
93
94 local_apic_id = Param.UInt8(0, 'local APIC id')
95 local_apic_version = Param.UInt8(0,
96 'bits 0-7 of the local APIC version register')
97 enable = Param.Bool(True, 'if this processor is usable')
98 bootstrap = Param.Bool(False, 'if this is the bootstrap processor')
99
100 stepping = Param.UInt8(0, 'Processor stepping')
101 model = Param.UInt8(0, 'Processor model')
102 family = Param.UInt8(0, 'Processor family')
103
104 feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction')
105
106class X86IntelMPBus(X86IntelMPBaseConfigEntry):
107 type = 'X86IntelMPBus'
108 cxx_class = 'X86ISA::IntelMP::Bus'
109
110 bus_id = Param.UInt8(0, 'bus id assigned by the bios')
111 bus_type = Param.String("", 'string that identify the bus type')
112 # Legal values for bus_type are:
113 #
114 # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII",
115 # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME",
116 # "XPRESS"
117
118class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
119 type = 'X86IntelMPIOAPIC'
120 cxx_class = 'X86ISA::IntelMP::IOAPIC'
121
122 id = Param.UInt8(0, 'id of this APIC')
123 version = Param.UInt8(0, 'bits 0-7 of the version register')
124
125 enable = Param.Bool(True, 'if this APIC is usable')
126
127 address = Param.UInt32(0xfec00000, 'address of this APIC')
128
129class X86IntelMPInterruptType(Enum):
130 map = {'INT' : 0,
131 'NMI' : 1,
132 'SMI' : 2,
133 'ExtInt' : 3
134 }
135
136class X86IntelMPPolarity(Enum):
137 map = {'ConformPolarity' : 0,
138 'ActiveHigh' : 1,
139 'ActiveLow' : 3
140 }
141
142class X86IntelMPTriggerMode(Enum):
143 map = {'ConformTrigger' : 0,
144 'EdgeTrigger' : 1,
145 'LevelTrigger' : 3
146 }
147
148class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
149 type = 'X86IntelMPIOIntAssignment'
150 cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
151
152 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
153
154 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
155 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
156
157 source_bus_id = Param.UInt8(0,
158 'id of the bus from which the interrupt signal comes')
159 source_bus_irq = Param.UInt8(0,
160 'which interrupt signal from the source bus')
161
162 dest_io_apic_id = Param.UInt8(0,
163 'id of the IO APIC the interrupt is going to')
164 dest_io_apic_intin = Param.UInt8(0,
165 'the INTIN pin on the IO APIC the interrupt is connected to')
166
167class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
168 type = 'X86IntelMPLocalIntAssignment'
169 cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
170
171 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
172
173 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
174 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
175
176 source_bus_id = Param.UInt8(0,
177 'id of the bus from which the interrupt signal comes')
178 source_bus_irq = Param.UInt8(0,
179 'which interrupt signal from the source bus')
180
181 dest_local_apic_id = Param.UInt8(0,
182 'id of the local APIC the interrupt is going to')
183 dest_local_apic_intin = Param.UInt8(0,
184 'the INTIN pin on the local APIC the interrupt is connected to')
185
186class X86IntelMPAddressType(Enum):
187 map = {"IOAddress" : 0,
188 "MemoryAddress" : 1,
189 "PrefetchAddress" : 2
190 }
191
192class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
193 type = 'X86IntelMPAddrSpaceMapping'
194 cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
195
196 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
197 address_type = Param.X86IntelMPAddressType('IOAddress',
198 'address type used to access bus')
199 address = Param.Addr(0, 'starting address of the mapping')
200 length = Param.UInt64(0, 'length of mapping in bytes')
201
202class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
203 type = 'X86IntelMPBusHierarchy'
204 cxx_class = 'X86ISA::IntelMP::BusHierarchy'
205
206 bus_id = Param.UInt8(0, 'id of the bus being described')
207 subtractive_decode = Param.Bool(False,
208 'whether this bus contains all addresses not used by its children')
209 parent_bus = Param.UInt8(0, 'bus id of this busses parent')
210
211class X86IntelMPRangeList(Enum):
212 map = {"ISACompatible" : 0,
213 "VGACompatible" : 1
214 }
215
216class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
217 type = 'X86IntelMPCompatAddrSpaceMod'
218 cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
219
220 bus_id = Param.UInt8(0, 'id of the bus being described')
221 add = Param.Bool(False,
222 'if the range should be added to the original mapping')
223 range_list = Param.X86IntelMPRangeList('ISACompatible',
224 'which predefined range of addresses to use')