X86TLB.py (5610:0e1e9c186769) | X86TLB.py (5628:f79155751e1d) |
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1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 40 unchanged lines hidden (view full) --- 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 56from MemObject import MemObject | 1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 40 unchanged lines hidden (view full) --- 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 56from MemObject import MemObject |
57from m5.SimObject import SimObject | |
58from m5.params import * 59from m5.proxy import * 60from m5 import build_env | 57from m5.params import * 58from m5.proxy import * 59from m5 import build_env |
60from BaseTLB import BaseTLB |
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61 62if build_env['FULL_SYSTEM']: 63 class X86PagetableWalker(MemObject): 64 type = 'X86PagetableWalker' 65 cxx_class = 'X86ISA::Walker' 66 port = Port("Port for the hardware table walker") 67 system = Param.System(Parent.any, "system object") 68 | 61 62if build_env['FULL_SYSTEM']: 63 class X86PagetableWalker(MemObject): 64 type = 'X86PagetableWalker' 65 cxx_class = 'X86ISA::Walker' 66 port = Port("Port for the hardware table walker") 67 system = Param.System(Parent.any, "system object") 68 |
69class X86TLB(SimObject): | 69class X86TLB(BaseTLB): |
70 type = 'X86TLB' 71 abstract = True 72 size = Param.Int("TLB size") 73 if build_env['FULL_SYSTEM']: 74 walker = Param.X86PagetableWalker(\ 75 X86PagetableWalker(), "page table walker") 76 77class X86DTB(X86TLB): 78 type = 'X86DTB' 79 cxx_class = 'X86ISA::DTB' 80 size = 64 81 82class X86ITB(X86TLB): 83 type = 'X86ITB' 84 cxx_class = 'X86ISA::ITB' 85 size = 64 | 70 type = 'X86TLB' 71 abstract = True 72 size = Param.Int("TLB size") 73 if build_env['FULL_SYSTEM']: 74 walker = Param.X86PagetableWalker(\ 75 X86PagetableWalker(), "page table walker") 76 77class X86DTB(X86TLB): 78 type = 'X86DTB' 79 cxx_class = 'X86ISA::DTB' 80 size = 64 81 82class X86ITB(X86TLB): 83 type = 'X86ITB' 84 cxx_class = 'X86ISA::ITB' 85 size = 64 |