X86TLB.py (5237:6c819dbe8045) X86TLB.py (5245:d94bb8af9f76)
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# Redistribution and use of this software in source and binary forms,
5# with or without modification, are permitted provided that the
6# following conditions are met:
7#
8# The software must be used only for Non-Commercial Use which means any

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49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53#
54# Authors: Gabe Black
55
56from MemObject import MemObject
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# Redistribution and use of this software in source and binary forms,
5# with or without modification, are permitted provided that the
6# following conditions are met:
7#
8# The software must be used only for Non-Commercial Use which means any

--- 40 unchanged lines hidden (view full) ---

49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53#
54# Authors: Gabe Black
55
56from MemObject import MemObject
57from m5.SimObject import SimObject
57from m5.params import *
58from m5.proxy import *
58from m5.params import *
59from m5.proxy import *
60from m5 import build_env
59
61
60class X86TLB(MemObject):
62if build_env['FULL_SYSTEM']:
63 class X86PagetableWalker(MemObject):
64 type = 'X86PagetableWalker'
65 cxx_namespace = 'X86ISA'
66 cxx_class = 'Walker'
67 port = Port("Port for the hardware table walker")
68 system = Param.System(Parent.any, "system object")
69
70class X86TLB(SimObject):
61 type = 'X86TLB'
71 type = 'X86TLB'
72 cxx_namespace = 'X86ISA'
73 cxx_class = 'TLB'
62 abstract = True
63 size = Param.Int("TLB size")
74 abstract = True
75 size = Param.Int("TLB size")
64 walker_port = Port("Port for the hardware table walker")
65 system = Param.System(Parent.any, "system object")
76 if build_env['FULL_SYSTEM']:
77 walker = Param.X86PagetableWalker(\
78 X86PagetableWalker(), "page table walker")
66
67class X86DTB(X86TLB):
68 type = 'X86DTB'
69 cxx_namespace = 'X86ISA'
70 cxx_class = 'DTB'
71
72 size = 64
73
74class X86ITB(X86TLB):
75 type = 'X86ITB'
76 cxx_namespace = 'X86ISA'
77 cxx_class = 'ITB'
78
79 size = 64
79
80class X86DTB(X86TLB):
81 type = 'X86DTB'
82 cxx_namespace = 'X86ISA'
83 cxx_class = 'DTB'
84
85 size = 64
86
87class X86ITB(X86TLB):
88 type = 'X86ITB'
89 cxx_namespace = 'X86ISA'
90 cxx_class = 'ITB'
91
92 size = 64