X86TLB.py (13665:9c7fe3811b88) | X86TLB.py (13892:0182a0601f66) |
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1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Gabe Black 37 38from m5.params import * 39from m5.proxy import * 40 41from m5.objects.BaseTLB import BaseTLB | 1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Gabe Black 37 38from m5.params import * 39from m5.proxy import * 40 41from m5.objects.BaseTLB import BaseTLB |
42from m5.objects.MemObject import MemObject | 42from m5.objects.ClockedObject import ClockedObject |
43 | 43 |
44class X86PagetableWalker(MemObject): | 44class X86PagetableWalker(ClockedObject): |
45 type = 'X86PagetableWalker' 46 cxx_class = 'X86ISA::Walker' 47 cxx_header = 'arch/x86/pagetable_walker.hh' 48 port = MasterPort("Port for the hardware table walker") 49 system = Param.System(Parent.any, "system object") 50 num_squash_per_cycle = Param.Unsigned(4, 51 "Number of outstanding walks that can be squashed per cycle") 52 53class X86TLB(BaseTLB): 54 type = 'X86TLB' 55 cxx_class = 'X86ISA::TLB' 56 cxx_header = 'arch/x86/tlb.hh' 57 size = Param.Unsigned(64, "TLB size") 58 walker = Param.X86PagetableWalker(\ 59 X86PagetableWalker(), "page table walker") | 45 type = 'X86PagetableWalker' 46 cxx_class = 'X86ISA::Walker' 47 cxx_header = 'arch/x86/pagetable_walker.hh' 48 port = MasterPort("Port for the hardware table walker") 49 system = Param.System(Parent.any, "system object") 50 num_squash_per_cycle = Param.Unsigned(4, 51 "Number of outstanding walks that can be squashed per cycle") 52 53class X86TLB(BaseTLB): 54 type = 'X86TLB' 55 cxx_class = 'X86ISA::TLB' 56 cxx_header = 'arch/x86/tlb.hh' 57 size = Param.Unsigned(64, "TLB size") 58 walker = Param.X86PagetableWalker(\ 59 X86PagetableWalker(), "page table walker") |