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> from m5.SimObject import SimObject
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> from m5 import build_env
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< class X86TLB(MemObject):
---
> if build_env['FULL_SYSTEM']:
> class X86PagetableWalker(MemObject):
> type = 'X86PagetableWalker'
> cxx_namespace = 'X86ISA'
> cxx_class = 'Walker'
> port = Port("Port for the hardware table walker")
> system = Param.System(Parent.any, "system object")
>
> class X86TLB(SimObject):
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> cxx_namespace = 'X86ISA'
> cxx_class = 'TLB'
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< walker_port = Port("Port for the hardware table walker")
< system = Param.System(Parent.any, "system object")
---
> if build_env['FULL_SYSTEM']:
> walker = Param.X86PagetableWalker(\
> X86PagetableWalker(), "page table walker")