vtophys.cc (2680:246e7104f744) | vtophys.cc (3529:1e2a78acb25d) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Ali Saidi 31 */ 32 33#include <string> 34 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Ali Saidi 31 */ 32 33#include <string> 34 |
35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" | 35#include "arch/sparc/vtophys.hh" |
37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std; | 36#include "base/chunk_generator.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "mem/vport.hh" 40 41using namespace std; |
43using namespace AlphaISA; | |
44 | 42 |
45AlphaISA::PageTableEntry 46AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) | 43namespace SparcISA |
47{ | 44{ |
48 Addr level1_pte = ptbr + vaddr.level1(); 49 AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); 50 if (!level1.valid()) { 51 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 52 return 0; | 45 PageTableEntry kernel_pte_lookup(FunctionalPort *mem, 46 Addr ptbr, VAddr vaddr) 47 { 48 PageTableEntry pte(4); 49 return pte; |
53 } 54 | 50 } 51 |
55 Addr level2_pte = level1.paddr() + vaddr.level2(); 56 AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); 57 if (!level2.valid()) { 58 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 59 return 0; | 52 Addr vtophys(Addr vaddr) 53 { 54 return vaddr; |
60 } 61 | 55 } 56 |
62 Addr level3_pte = level2.paddr() + vaddr.level3(); 63 AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); 64 if (!level3.valid()) { 65 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 66 return 0; | 57 Addr vtophys(ThreadContext *tc, Addr addr) 58 { 59 return addr; |
67 } | 60 } |
68 return level3; 69} | |
70 | 61 |
71Addr 72AlphaISA::vtophys(Addr vaddr) 73{ 74 Addr paddr = 0; 75 if (AlphaISA::IsUSeg(vaddr)) 76 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); 77 else if (AlphaISA::IsK0Seg(vaddr)) 78 paddr = AlphaISA::K0Seg2Phys(vaddr); 79 else 80 panic("vtophys: ptbr is not set on virtual lookup"); | |
81 | 62 |
82 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); | 63 void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) 64 { 65 } |
83 | 66 |
84 return paddr; 85} | 67 void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) 68 { 69 } |
86 | 70 |
87Addr 88AlphaISA::vtophys(ThreadContext *tc, Addr addr) 89{ 90 AlphaISA::VAddr vaddr = addr; 91 Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); 92 Addr paddr = 0; 93 //@todo Andrew couldn't remember why he commented some of this code 94 //so I put it back in. Perhaps something to do with gdb debugging? 95 if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) { 96 paddr = vaddr & ~ULL(1); 97 } else { 98 if (AlphaISA::IsK0Seg(vaddr)) { 99 paddr = AlphaISA::K0Seg2Phys(vaddr); 100 } else if (!ptbr) { 101 paddr = vaddr; 102 } else { 103 AlphaISA::PageTableEntry pte = 104 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 105 if (pte.valid()) 106 paddr = pte.paddr() | vaddr.offset(); 107 } | 71 void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) 72 { |
108 } 109 | 73 } 74 |
110 111 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 112 113 return paddr; 114} 115 116 117void 118AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) 119{ 120 uint8_t *dst = (uint8_t *)dest; 121 VirtualPort *vp = tc->getVirtPort(tc); 122 123 vp->readBlob(src, dst, cplen); 124 125 tc->delVirtPort(vp); 126 127} 128 129void 130AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) 131{ 132 uint8_t *src = (uint8_t *)source; 133 VirtualPort *vp = tc->getVirtPort(tc); 134 135 vp->writeBlob(dest, src, cplen); 136 137 tc->delVirtPort(vp); 138} 139 140void 141AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) 142{ 143 int len = 0; 144 VirtualPort *vp = tc->getVirtPort(tc); 145 146 do { 147 vp->readBlob(vaddr++, (uint8_t*)dst++, 1); 148 len++; 149 } while (len < maxlen && dst[len] != 0 ); 150 151 tc->delVirtPort(vp); 152 dst[len] = 0; 153} 154 155void 156AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) 157{ 158 VirtualPort *vp = tc->getVirtPort(tc); 159 for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); 160 gen.next()) | 75 void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) |
161 { | 76 { |
162 vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); 163 src += gen.size(); | |
164 } | 77 } |
165 tc->delVirtPort(vp); | |
166} | 78} |