1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <string> 32 33#include "arch/sparc/vtophys.hh" 34#include "arch/sparc/tlb.hh" 35#include "base/compiler.hh" 36#include "base/chunk_generator.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "mem/vport.hh" 40 41using namespace std; 42
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <string> 32 33#include "arch/sparc/vtophys.hh" 34#include "arch/sparc/tlb.hh" 35#include "base/compiler.hh" 36#include "base/chunk_generator.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "mem/vport.hh" 40 41using namespace std; 42
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43namespace SparcISA
| 43namespace SparcISA { 44 45Addr 46vtophys(Addr vaddr)
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44{
| 47{
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45 Addr vtophys(Addr vaddr) 46 { 47 // In SPARC it's almost always impossible to turn a VA->PA w/o a context 48 // The only times we can kinda do it are if we have a SegKPM mapping 49 // and can find the real address in the tlb or we have a physical 50 // adddress already (beacuse we are looking at the hypervisor) 51 // Either case is rare, so we'll just panic.
| 48 // In SPARC it's almost always impossible to turn a VA->PA w/o a 49 // context The only times we can kinda do it are if we have a 50 // SegKPM mapping and can find the real address in the tlb or we 51 // have a physical adddress already (beacuse we are looking at the 52 // hypervisor) Either case is rare, so we'll just panic.
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52
| 53
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53 panic("vtophys() without context on SPARC largly worthless\n"); 54 M5_DUMMY_RETURN 55 }
| 54 panic("vtophys() without context on SPARC largly worthless\n"); 55 M5_DUMMY_RETURN; 56}
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56
| 57
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57 Addr vtophys(ThreadContext *tc, Addr addr) 58 { 59 // Here we have many options and are really implementing something like 60 // a fill handler to find the address since there isn't a multilevel 61 // table for us to walk around. 62 // 63 // 1. We are currently hyperpriv, return the address unmodified 64 // 2. The mmu is off return(ra->pa) 65 // 3. We are currently priv, use ctx0* tsbs to find the page 66 // 4. We are not priv, use ctxN0* tsbs to find the page 67 // For all accesses we check the tlbs first since it's possible that 68 // long standing pages (e.g. locked kernel mappings) won't be in the tsb 69 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
| 58Addr 59vtophys(ThreadContext *tc, Addr addr) 60{ 61 // Here we have many options and are really implementing something like 62 // a fill handler to find the address since there isn't a multilevel 63 // table for us to walk around. 64 // 65 // 1. We are currently hyperpriv, return the address unmodified 66 // 2. The mmu is off return(ra->pa) 67 // 3. We are currently priv, use ctx0* tsbs to find the page 68 // 4. We are not priv, use ctxN0* tsbs to find the page 69 // For all accesses we check the tlbs first since it's possible that 70 // long standing pages (e.g. locked kernel mappings) won't be in the tsb 71 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
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70
| 72
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71 bool hpriv = bits(tlbdata,0,0); 72 //bool priv = bits(tlbdata,2,2); 73 bool addr_mask = bits(tlbdata,3,3); 74 bool data_real = !bits(tlbdata,5,5); 75 bool inst_real = !bits(tlbdata,4,4); 76 bool ctx_zero = bits(tlbdata,18,16) > 0; 77 int part_id = bits(tlbdata,15,8); 78 int pri_context = bits(tlbdata,47,32); 79 //int sec_context = bits(tlbdata,63,48);
| 73 bool hpriv = bits(tlbdata,0,0); 74 //bool priv = bits(tlbdata,2,2); 75 bool addr_mask = bits(tlbdata,3,3); 76 bool data_real = !bits(tlbdata,5,5); 77 bool inst_real = !bits(tlbdata,4,4); 78 bool ctx_zero = bits(tlbdata,18,16) > 0; 79 int part_id = bits(tlbdata,15,8); 80 int pri_context = bits(tlbdata,47,32); 81 //int sec_context = bits(tlbdata,63,48);
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80
| 82
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81 FunctionalPort *mem = tc->getPhysPort(); 82 ITB* itb = tc->getITBPtr(); 83 DTB* dtb = tc->getDTBPtr(); 84 TlbEntry* tbe; 85 PageTableEntry pte; 86 Addr tsbs[4]; 87 Addr va_tag; 88 TteTag ttetag;
| 83 FunctionalPort *mem = tc->getPhysPort(); 84 ITB* itb = tc->getITBPtr(); 85 DTB* dtb = tc->getDTBPtr(); 86 TlbEntry* tbe; 87 PageTableEntry pte; 88 Addr tsbs[4]; 89 Addr va_tag; 90 TteTag ttetag;
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89
| 91
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90 if (hpriv) 91 return addr;
| 92 if (hpriv) 93 return addr;
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92
| 94
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93 if (addr_mask) 94 addr = addr & VAddrAMask;
| 95 if (addr_mask) 96 addr = addr & VAddrAMask;
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95
| 97
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96 tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , false); 97 if (tbe) goto foundtbe;
| 98 tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , 99 false); 100 if (tbe) 101 goto foundtbe;
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98
| 102
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99 tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, false); 100 if (tbe) goto foundtbe;
| 103 tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, 104 false); 105 if (tbe) 106 goto foundtbe;
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101
| 107
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102 // We didn't find it in the tlbs, so lets look at the TSBs 103 dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs); 104 va_tag = bits(addr, 63, 22); 105 for (int x = 0; x < 4; x++) { 106 ttetag = betoh(mem->read<uint64_t>(tsbs[x])); 107 if (ttetag.valid() && ttetag.va() == va_tag) { 108 pte.populate(betoh(mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t)), 109 PageTableEntry::sun4v); // I think it's sun4v at least! 110 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", addr, 111 pte.paddrMask() | addr & pte.sizeMask()); 112 goto foundpte; 113 }
| 108 // We didn't find it in the tlbs, so lets look at the TSBs 109 dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs); 110 va_tag = bits(addr, 63, 22); 111 for (int x = 0; x < 4; x++) { 112 ttetag = betoh(mem->read(tsbs[x])); 113 if (ttetag.valid() && ttetag.va() == va_tag) { 114 uint64_t entry = mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t); 115 // I think it's sun4v at least! 116 pte.populate(betoh(entry), PageTableEntry::sun4v); 117 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", 118 addr, pte.translate(addr)); 119 goto foundpte;
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114 }
| 120 }
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115 panic("couldn't translate %#x\n", addr); 116 117foundtbe: 118 pte = tbe->pte; 119 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr, 120 pte.paddrMask() | addr & pte.sizeMask()); 121foundpte: 122 return pte.paddrMask() | addr & pte.sizeMask();
| |
123 }
| 121 }
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| 122 panic("couldn't translate %#x\n", addr); 123 124 foundtbe: 125 pte = tbe->pte; 126 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr, 127 pte.translate(addr)); 128 foundpte: 129 return pte.translate(addr);
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124}
| 130}
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| 131 132} /* namespace SparcISA */
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| |