1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <string>
32
33#include "arch/sparc/vtophys.hh"
34#include "arch/sparc/tlb.hh"
35#include "base/compiler.hh"
36#include "base/chunk_generator.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "mem/vport.hh"
40
41using namespace std;
42
43namespace SparcISA
44{
45 Addr vtophys(Addr vaddr)
46 {
47 // In SPARC it's almost always impossible to turn a VA->PA w/o a context
48 // The only times we can kinda do it are if we have a SegKPM mapping
49 // and can find the real address in the tlb or we have a physical
50 // adddress already (beacuse we are looking at the hypervisor)
51 // Either case is rare, so we'll just panic.
52
53 panic("vtophys() without context on SPARC largly worthless\n");
54 M5_DUMMY_RETURN
55 }
56
57 Addr vtophys(ThreadContext *tc, Addr addr)
58 {
59 // Here we have many options and are really implementing something like
60 // a fill handler to find the address since there isn't a multilevel
61 // table for us to walk around.
62 //
63 // 1. We are currently hyperpriv, return the address unmodified
64 // 2. The mmu is off return(ra->pa)
65 // 3. We are currently priv, use ctx0* tsbs to find the page
66 // 4. We are not priv, use ctxN0* tsbs to find the page
67 // For all accesses we check the tlbs first since it's possible that
68 // long standing pages (e.g. locked kernel mappings) won't be in the tsb
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <string>
32
33#include "arch/sparc/vtophys.hh"
34#include "arch/sparc/tlb.hh"
35#include "base/compiler.hh"
36#include "base/chunk_generator.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "mem/vport.hh"
40
41using namespace std;
42
43namespace SparcISA
44{
45 Addr vtophys(Addr vaddr)
46 {
47 // In SPARC it's almost always impossible to turn a VA->PA w/o a context
48 // The only times we can kinda do it are if we have a SegKPM mapping
49 // and can find the real address in the tlb or we have a physical
50 // adddress already (beacuse we are looking at the hypervisor)
51 // Either case is rare, so we'll just panic.
52
53 panic("vtophys() without context on SPARC largly worthless\n");
54 M5_DUMMY_RETURN
55 }
56
57 Addr vtophys(ThreadContext *tc, Addr addr)
58 {
59 // Here we have many options and are really implementing something like
60 // a fill handler to find the address since there isn't a multilevel
61 // table for us to walk around.
62 //
63 // 1. We are currently hyperpriv, return the address unmodified
64 // 2. The mmu is off return(ra->pa)
65 // 3. We are currently priv, use ctx0* tsbs to find the page
66 // 4. We are not priv, use ctxN0* tsbs to find the page
67 // For all accesses we check the tlbs first since it's possible that
68 // long standing pages (e.g. locked kernel mappings) won't be in the tsb
|
70
71 bool hpriv = bits(tlbdata,0,0);
72 //bool priv = bits(tlbdata,2,2);
73 bool addr_mask = bits(tlbdata,3,3);
74 bool data_real = !bits(tlbdata,5,5);
75 bool inst_real = !bits(tlbdata,4,4);
76 bool ctx_zero = bits(tlbdata,18,16) > 0;
77 int part_id = bits(tlbdata,15,8);
78 int pri_context = bits(tlbdata,47,32);
79 //int sec_context = bits(tlbdata,63,48);
80
81 FunctionalPort *mem = tc->getPhysPort();
82 ITB* itb = tc->getITBPtr();
83 DTB* dtb = tc->getDTBPtr();
84 TlbEntry* tbe;
85 PageTableEntry pte;
86 Addr tsbs[4];
87 Addr va_tag;
88 TteTag ttetag;
89
90 if (hpriv)
91 return addr;
92
93 if (addr_mask)
94 addr = addr & VAddrAMask;
95
96 tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , false);
97 if (tbe) goto foundtbe;
98
99 tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, false);
100 if (tbe) goto foundtbe;
101
102 // We didn't find it in the tlbs, so lets look at the TSBs
103 dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
104 va_tag = bits(addr, 63, 22);
105 for (int x = 0; x < 4; x++) {
106 ttetag = betoh(mem->read<uint64_t>(tsbs[x]));
107 if (ttetag.valid() && ttetag.va() == va_tag) {
108 pte.populate(betoh(mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t)),
109 PageTableEntry::sun4v); // I think it's sun4v at least!
110 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", addr,
111 pte.paddrMask() | addr & pte.sizeMask());
112 goto foundpte;
113 }
114 }
115 panic("couldn't translate %#x\n", addr);
116
117foundtbe:
118 pte = tbe->pte;
119 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
120 pte.paddrMask() | addr & pte.sizeMask());
121foundpte:
122 return pte.paddrMask() | addr & pte.sizeMask();
123 }
124}
| 70
71 bool hpriv = bits(tlbdata,0,0);
72 //bool priv = bits(tlbdata,2,2);
73 bool addr_mask = bits(tlbdata,3,3);
74 bool data_real = !bits(tlbdata,5,5);
75 bool inst_real = !bits(tlbdata,4,4);
76 bool ctx_zero = bits(tlbdata,18,16) > 0;
77 int part_id = bits(tlbdata,15,8);
78 int pri_context = bits(tlbdata,47,32);
79 //int sec_context = bits(tlbdata,63,48);
80
81 FunctionalPort *mem = tc->getPhysPort();
82 ITB* itb = tc->getITBPtr();
83 DTB* dtb = tc->getDTBPtr();
84 TlbEntry* tbe;
85 PageTableEntry pte;
86 Addr tsbs[4];
87 Addr va_tag;
88 TteTag ttetag;
89
90 if (hpriv)
91 return addr;
92
93 if (addr_mask)
94 addr = addr & VAddrAMask;
95
96 tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context , false);
97 if (tbe) goto foundtbe;
98
99 tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context, false);
100 if (tbe) goto foundtbe;
101
102 // We didn't find it in the tlbs, so lets look at the TSBs
103 dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
104 va_tag = bits(addr, 63, 22);
105 for (int x = 0; x < 4; x++) {
106 ttetag = betoh(mem->read<uint64_t>(tsbs[x]));
107 if (ttetag.valid() && ttetag.va() == va_tag) {
108 pte.populate(betoh(mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t)),
109 PageTableEntry::sun4v); // I think it's sun4v at least!
110 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n", addr,
111 pte.paddrMask() | addr & pte.sizeMask());
112 goto foundpte;
113 }
114 }
115 panic("couldn't translate %#x\n", addr);
116
117foundtbe:
118 pte = tbe->pte;
119 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
120 pte.paddrMask() | addr & pte.sizeMask());
121foundpte:
122 return pte.paddrMask() | addr & pte.sizeMask();
123 }
124}
|