utility.hh (7572:3d72ff41f9d2) utility.hh (7627:3b0c4b819651)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45
46 static inline bool
47 inUserMode(ThreadContext *tc)
48 {
49 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
50 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
51 }
52
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 36 unchanged lines hidden (view full) ---

45
46 static inline bool
47 inUserMode(ThreadContext *tc)
48 {
49 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
50 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
51 }
52
53 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
54 panic("register classification not implemented");
55 return false;
56 }
57
58 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return false;
61 }
62
63 inline bool isCallerSaveFloatRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return false;
66 }
67
68 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 // Instruction address compression hooks
74 inline Addr realPCToFetchPC(const Addr &addr)
75 {
76 return addr;
77 }
78
79 inline Addr fetchPCToRealPC(const Addr &addr)
80 {
81 return addr;
82 }
83
84 // the size of "fetched" instructions (not necessarily the size
85 // of real instructions for PISA)
86 inline size_t fetchInstSize()
87 {
88 return sizeof(MachInst);
89 }
90
91 /**
92 * Function to insure ISA semantics about 0 registers.
93 * @param tc The thread context.
94 */
95 template <class TC>
96 void zeroRegisters(TC *tc);
97
98 inline void

--- 27 unchanged lines hidden --- 		53 /**
54 * Function to insure ISA semantics about 0 registers.
55 * @param tc The thread context.
56 */
57 template <class TC>
58 void zeroRegisters(TC *tc);
59
60 inline void

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