utility.hh (6335:a08470cb53e5) utility.hh (7572:3d72ff41f9d2)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/sparc/registers.hh"
37#include "arch/sparc/tlb.hh"
38#include "base/misc.hh"
39#include "base/bitfield.hh"
40#include "cpu/thread_context.hh"
41
42namespace SparcISA
43{
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/sparc/registers.hh"
37#include "arch/sparc/tlb.hh"
38#include "base/misc.hh"
39#include "base/bitfield.hh"
40#include "cpu/thread_context.hh"
41
42namespace SparcISA
43{
44
45
46 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
47
48 static inline bool
49 inUserMode(ThreadContext *tc)
50 {
51 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
52 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
53 }

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92
93 /**
94 * Function to insure ISA semantics about 0 registers.
95 * @param tc The thread context.
96 */
97 template <class TC>
98 void zeroRegisters(TC *tc);
99
44 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46 static inline bool
47 inUserMode(ThreadContext *tc)
48 {
49 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
50 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
51 }

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90
91 /**
92 * Function to insure ISA semantics about 0 registers.
93 * @param tc The thread context.
94 */
95 template <class TC>
96 void zeroRegisters(TC *tc);
97
100 inline void initCPU(ThreadContext *tc, int cpuId)
98 inline void
99 initCPU(ThreadContext *tc, int cpuId)
101 {
102 static Fault por = new PowerOnReset();
103 if (cpuId == 0)
104 por->invoke(tc);
105
106 }
107
100 {
101 static Fault por = new PowerOnReset();
102 if (cpuId == 0)
103 por->invoke(tc);
104
105 }
106
108 inline void startupCPU(ThreadContext *tc, int cpuId)
107 inline void
108 startupCPU(ThreadContext *tc, int cpuId)
109 {
110#if FULL_SYSTEM
111 // Other CPUs will get activated by IPIs
112 if (cpuId == 0)
113 tc->activate(0);
114#else
115 tc->activate(0);
116#endif
117 }
118
119 void copyRegs(ThreadContext *src, ThreadContext *dest);
120
121 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
122
123} // namespace SparcISA
124
125#endif
109 {
110#if FULL_SYSTEM
111 // Other CPUs will get activated by IPIs
112 if (cpuId == 0)
113 tc->activate(0);
114#else
115 tc->activate(0);
116#endif
117 }
118
119 void copyRegs(ThreadContext *src, ThreadContext *dest);
120
121 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
122
123} // namespace SparcISA
124
125#endif