utility.hh (4182:5b2c0d266107) utility.hh (4194:af4f6022394b)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43
44 static inline bool
45 inUserMode(ThreadContext *tc)
46 {
47 return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
48 tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
49 }
50
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43
44 static inline bool
45 inUserMode(ThreadContext *tc)
46 {
47 return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
48 tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
49 }
50
51 inline ExtMachInst
52 makeExtMI(MachInst inst, ThreadContext * xc) {
53 ExtMachInst emi = (MachInst) inst;
54 //The I bit, bit 13, is used to figure out where the ASI
55 //should come from. Use that in the ExtMachInst. This is
56 //slightly redundant, but it removes the need to put a condition
57 //into all the execute functions
58 if(inst & (1 << 13))
59 emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
60 << (sizeof(MachInst) * 8));
61 else
62 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
63 << (sizeof(MachInst) * 8));
64 return emi;
65 }
66
51 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
52 panic("register classification not implemented");
53 return false;
54 }
55
56 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
57 panic("register classification not implemented");
58 return false;

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91 * @param tc The thread context.
92 */
93 template <class TC>
94 void zeroRegisters(TC *tc);
95
96 inline void initCPU(ThreadContext *tc, int cpuId)
97 {
98 static Fault por = new PowerOnReset();
67 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
68 panic("register classification not implemented");
69 return false;
70 }
71
72 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
73 panic("register classification not implemented");
74 return false;

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107 * @param tc The thread context.
108 */
109 template <class TC>
110 void zeroRegisters(TC *tc);
111
112 inline void initCPU(ThreadContext *tc, int cpuId)
113 {
114 static Fault por = new PowerOnReset();
99 por->invoke(tc);
115 if (cpuId == 0)
116 por->invoke(tc);
117
100 }
101
118 }
119
120 inline void startupCPU(ThreadContext *tc, int cpuId)
121 {
122#if FULL_SYSTEM
123 // Other CPUs will get activated by IPIs
124 if (cpuId == 0)
125 tc->activate(0);
126#else
127 tc->activate(0);
128#endif
129 }
130
102} // namespace SparcISA
103
104#endif
131} // namespace SparcISA
132
133#endif