1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/misc.hh" 38#include "base/bitfield.hh" 39#include "cpu/static_inst.hh" 40#include "cpu/thread_context.hh" 41#include "sim/fault.hh" 42 43namespace SparcISA 44{ 45
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46 inline PCState
47 buildRetPC(const PCState &curPC, const PCState &callPC)
48 {
49 PCState ret = callPC;
50 ret.uEnd();
51 ret.pc(curPC.npc());
52 return ret;
53 }
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46inline PCState 47buildRetPC(const PCState &curPC, const PCState &callPC) 48{ 49 PCState ret = callPC; 50 ret.uEnd(); 51 ret.pc(curPC.npc()); 52 return ret; 53} |
54
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55 uint64_t
56 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
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55uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); |
56
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58 static inline bool
59 inUserMode(ThreadContext *tc)
60 {
61 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
62 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
63 }
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57static inline bool 58inUserMode(ThreadContext *tc) 59{ 60 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) || 61 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2))); 62} |
63
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65 /**
66 * Function to insure ISA semantics about 0 registers.
67 * @param tc The thread context.
68 */
69 template <class TC>
70 void zeroRegisters(TC *tc);
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64/** 65 * Function to insure ISA semantics about 0 registers. 66 * @param tc The thread context. 67 */ 68template 69void zeroRegisters(TC *tc); |
70
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72 void initCPU(ThreadContext *tc, int cpuId);
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71void initCPU(ThreadContext *tc, int cpuId); |
72
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74 inline void
75 startupCPU(ThreadContext *tc, int cpuId)
76 {
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73inline void 74startupCPU(ThreadContext *tc, int cpuId) 75{ |
76#if FULL_SYSTEM
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78 // Other CPUs will get activated by IPIs
79 if (cpuId == 0)
80 tc->activate(0);
81#else
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77 // Other CPUs will get activated by IPIs 78 if (cpuId == 0) |
79 tc->activate(0);
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80#else 81 tc->activate(0); |
82#endif
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84 }
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83} |
84
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86 void copyRegs(ThreadContext *src, ThreadContext *dest);
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85void copyRegs(ThreadContext *src, ThreadContext *dest); |
86
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88 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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87void copyMiscRegs(ThreadContext *src, ThreadContext *dest); |
88
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90 void skipFunction(ThreadContext *tc);
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89void skipFunction(ThreadContext *tc); |
90
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92 inline void
93 advancePC(PCState &pc, const StaticInstPtr inst)
94 {
95 inst->advancePC(pc);
96 }
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91inline void 92advancePC(PCState &pc, const StaticInstPtr inst) 93{ 94 inst->advancePC(pc); 95} |
96 97} // namespace SparcISA 98 99#endif
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