1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/isa_traits.hh" 35#include "base/misc.hh" |
36#include "base/bitfield.hh" |
37#include "cpu/thread_context.hh" 38 39namespace SparcISA 40{ 41 inline ExtMachInst 42 makeExtMI(MachInst inst, ThreadContext * xc) { 43 ExtMachInst emi = (unsigned MachInst) inst; 44 //The I bit, bit 13, is used to figure out where the ASI 45 //should come from. Use that in the ExtMachInst. This is 46 //slightly redundant, but it removes the need to put a condition 47 //into all the execute functions 48 if(inst & (1 << 13)) 49 emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI)) 50 << (sizeof(MachInst) * 8)); |
51 else 52 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) 53 << (sizeof(MachInst) * 8)); |
54 return emi; 55 } 56 57 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 58 panic("register classification not implemented"); 59 return false; 60 } 61 --- 43 unchanged lines hidden --- |