1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
|
36#include "arch/sparc/tlb.hh"
37#include "base/misc.hh"
38#include "base/bitfield.hh"
39#include "cpu/thread_context.hh"
40
41namespace SparcISA
42{
43
44
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
46
47 static inline bool
48 inUserMode(ThreadContext *tc)
49 {
50 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
51 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
52 }
53
54 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
55 panic("register classification not implemented");
56 return false;
57 }
58
59 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
60 panic("register classification not implemented");
61 return false;
62 }
63
64 inline bool isCallerSaveFloatRegister(unsigned int reg) {
65 panic("register classification not implemented");
66 return false;
67 }
68
69 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
70 panic("register classification not implemented");
71 return false;
72 }
73
74 // Instruction address compression hooks
75 inline Addr realPCToFetchPC(const Addr &addr)
76 {
77 return addr;
78 }
79
80 inline Addr fetchPCToRealPC(const Addr &addr)
81 {
82 return addr;
83 }
84
85 // the size of "fetched" instructions (not necessarily the size
86 // of real instructions for PISA)
87 inline size_t fetchInstSize()
88 {
89 return sizeof(MachInst);
90 }
91
92 /**
93 * Function to insure ISA semantics about 0 registers.
94 * @param tc The thread context.
95 */
96 template <class TC>
97 void zeroRegisters(TC *tc);
98
99 inline void initCPU(ThreadContext *tc, int cpuId)
100 {
101 static Fault por = new PowerOnReset();
102 if (cpuId == 0)
103 por->invoke(tc);
104
105 }
106
107 inline void startupCPU(ThreadContext *tc, int cpuId)
108 {
109#if FULL_SYSTEM
110 // Other CPUs will get activated by IPIs
111 if (cpuId == 0)
112 tc->activate(0);
113#else
114 tc->activate(0);
115#endif
116 }
117
118} // namespace SparcISA
119
120#endif
| 37#include "arch/sparc/tlb.hh"
38#include "base/misc.hh"
39#include "base/bitfield.hh"
40#include "cpu/thread_context.hh"
41
42namespace SparcISA
43{
44
45
46 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
47
48 static inline bool
49 inUserMode(ThreadContext *tc)
50 {
51 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
52 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
53 }
54
55 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
56 panic("register classification not implemented");
57 return false;
58 }
59
60 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
61 panic("register classification not implemented");
62 return false;
63 }
64
65 inline bool isCallerSaveFloatRegister(unsigned int reg) {
66 panic("register classification not implemented");
67 return false;
68 }
69
70 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
71 panic("register classification not implemented");
72 return false;
73 }
74
75 // Instruction address compression hooks
76 inline Addr realPCToFetchPC(const Addr &addr)
77 {
78 return addr;
79 }
80
81 inline Addr fetchPCToRealPC(const Addr &addr)
82 {
83 return addr;
84 }
85
86 // the size of "fetched" instructions (not necessarily the size
87 // of real instructions for PISA)
88 inline size_t fetchInstSize()
89 {
90 return sizeof(MachInst);
91 }
92
93 /**
94 * Function to insure ISA semantics about 0 registers.
95 * @param tc The thread context.
96 */
97 template <class TC>
98 void zeroRegisters(TC *tc);
99
100 inline void initCPU(ThreadContext *tc, int cpuId)
101 {
102 static Fault por = new PowerOnReset();
103 if (cpuId == 0)
104 por->invoke(tc);
105
106 }
107
108 inline void startupCPU(ThreadContext *tc, int cpuId)
109 {
110#if FULL_SYSTEM
111 // Other CPUs will get activated by IPIs
112 if (cpuId == 0)
113 tc->activate(0);
114#else
115 tc->activate(0);
116#endif
117 }
118
119} // namespace SparcISA
120
121#endif
|