1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
|
34#include "arch/sparc/isa_traits.hh"
35#include "base/misc.hh"
36#include "base/bitfield.hh"
37#include "cpu/thread_context.hh"
38
39namespace SparcISA
40{
41 inline ExtMachInst
42 makeExtMI(MachInst inst, ThreadContext * xc) {
43 ExtMachInst emi = (unsigned MachInst) inst;
44 //The I bit, bit 13, is used to figure out where the ASI
45 //should come from. Use that in the ExtMachInst. This is
46 //slightly redundant, but it removes the need to put a condition
47 //into all the execute functions
48 if(inst & (1 << 13))
49 emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
50 << (sizeof(MachInst) * 8));
51 else
52 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
53 << (sizeof(MachInst) * 8));
54 return emi;
55 }
56
57 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
58 panic("register classification not implemented");
59 return false;
60 }
61
62 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
63 panic("register classification not implemented");
64 return false;
65 }
66
67 inline bool isCallerSaveFloatRegister(unsigned int reg) {
68 panic("register classification not implemented");
69 return false;
70 }
71
72 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
73 panic("register classification not implemented");
74 return false;
75 }
76
77 // Instruction address compression hooks
78 inline Addr realPCToFetchPC(const Addr &addr)
79 {
80 return addr;
81 }
82
83 inline Addr fetchPCToRealPC(const Addr &addr)
84 {
85 return addr;
86 }
87
88 // the size of "fetched" instructions (not necessarily the size
89 // of real instructions for PISA)
90 inline size_t fetchInstSize()
91 {
92 return sizeof(MachInst);
93 }
94
95 /**
96 * Function to insure ISA semantics about 0 registers.
97 * @param tc The thread context.
98 */
99 template <class TC>
100 void zeroRegisters(TC *tc);
101
| 35#include "arch/sparc/isa_traits.hh"
36#include "base/misc.hh"
37#include "base/bitfield.hh"
38#include "cpu/thread_context.hh"
39
40namespace SparcISA
41{
42 inline ExtMachInst
43 makeExtMI(MachInst inst, ThreadContext * xc) {
44 ExtMachInst emi = (unsigned MachInst) inst;
45 //The I bit, bit 13, is used to figure out where the ASI
46 //should come from. Use that in the ExtMachInst. This is
47 //slightly redundant, but it removes the need to put a condition
48 //into all the execute functions
49 if(inst & (1 << 13))
50 emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
51 << (sizeof(MachInst) * 8));
52 else
53 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
54 << (sizeof(MachInst) * 8));
55 return emi;
56 }
57
58 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return false;
61 }
62
63 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return false;
66 }
67
68 inline bool isCallerSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
74 panic("register classification not implemented");
75 return false;
76 }
77
78 // Instruction address compression hooks
79 inline Addr realPCToFetchPC(const Addr &addr)
80 {
81 return addr;
82 }
83
84 inline Addr fetchPCToRealPC(const Addr &addr)
85 {
86 return addr;
87 }
88
89 // the size of "fetched" instructions (not necessarily the size
90 // of real instructions for PISA)
91 inline size_t fetchInstSize()
92 {
93 return sizeof(MachInst);
94 }
95
96 /**
97 * Function to insure ISA semantics about 0 registers.
98 * @param tc The thread context.
99 */
100 template <class TC>
101 void zeroRegisters(TC *tc);
102
|